testsuite/synth: add a test for previous commit.

3 files changed, 62 insertions, 2 deletions

diff --git a/testsuite/synth/func01/func08.vhdl b/testsuite/synth/func01/func08.vhdl
new file mode 100644
index 000000000..d8f0e4d18
--- /dev/null
+++ b/testsuite/synth/func01/func08.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity func08 is
+  port (v : std_ulogic_vector (31 downto 0);
+        r : out integer);
+end func08;
+
+architecture behav of func08 is
+  function fls (val: std_ulogic_vector(31 downto 0)) return integer is
+    variable ret: integer;
+  begin
+    ret := 32;
+    for i in val'range loop
+      if val(i) = '1' then
+        ret := 31 - i;
+        exit;
+      end if;
+    end loop;
+
+    return ret;
+  end;
+begin
+  r <= fls(v);
+end behav;
diff --git a/testsuite/synth/func01/tb_func08.vhdl b/testsuite/synth/func01/tb_func08.vhdl
new file mode 100644
index 000000000..792d91992
--- /dev/null
+++ b/testsuite/synth/func01/tb_func08.vhdl
@@ -0,0 +1,34 @@
+entity tb_func08 is
+end tb_func08;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func08 is
+  signal v : std_ulogic_vector(31 downto 0);
+  signal r : integer;
+begin
+  dut: entity work.func08
+    port map (v, r);
+
+  process
+  begin
+    v <= x"00000000";
+    wait for 1 ns;
+    assert r = 32 severity failure;
+
+    v <= x"0000_0001";
+    wait for 1 ns;
+    assert r = 31 severity failure;
+
+    v <= x"8000_0000";
+    wait for 1 ns;
+    assert r = 0 severity failure;
+
+    v <= x"0001_00f0";
+    wait for 1 ns;
+    assert r = 15 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/testsuite.sh b/testsuite/synth/func01/testsuite.sh
index c87986336..7c9a78748 100755
--- a/testsuite/synth/func01/testsuite.sh
+++ b/testsuite/synth/func01/testsuite.sh
@@ -2,14 +2,14 @@
 
 . ../../testenv.sh
 
-for t in func01 func02 func03 func04 func05 func06 func07; do
+for t in func01 func02 func03 func04 func05 func06 func07 func08; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
 
     synth $t.vhdl -e $t > syn_$t.vhdl
     analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
     clean
 done