testsuite/synth: add more tests in func01.

9 files changed, 214 insertions, 1 deletions

diff --git a/testsuite/synth/func01/func04.vhdl b/testsuite/synth/func01/func04.vhdl
new file mode 100644
index 000000000..a7c5f2014
--- /dev/null
+++ b/testsuite/synth/func01/func04.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity func04 is
+  port (a : std_logic_vector (7 downto 0);
+        b : std_logic_vector (7 downto 0);
+        r : out std_logic_vector (7 downto 0));
+end func04;
+
+architecture behav of func04 is
+  function gen_mask (len : natural) return std_logic_vector is
+    variable res : std_logic_vector (len - 1 downto 0);
+  begin
+    res := (0 | 1 => '0', others => '1');
+    return res;
+  end gen_mask;
+  constant mask : std_logic_vector(7 downto 0) := not gen_mask (8);
+begin
+  r <= (a and mask) or (b and gen_mask (8));
+end behav;
+    
diff --git a/testsuite/synth/func01/func05.vhdl b/testsuite/synth/func01/func05.vhdl
new file mode 100644
index 000000000..e282b24a6
--- /dev/null
+++ b/testsuite/synth/func01/func05.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity func05 is
+  port (s : natural;
+        r : out std_logic_vector (15 downto 0));
+end func05;
+
+architecture behav of func05 is
+  function mapv (sel : natural) return std_logic_vector
+  is
+    variable res : std_logic_vector(15 downto 0) := (others => '0');
+  begin
+    if sel = 2 then
+      res := x"1234";
+    end if;
+    return res;
+  end mapv; 
+begin
+  r <= mapv (s);
+end behav;
+    
diff --git a/testsuite/synth/func01/func06.vhdl b/testsuite/synth/func01/func06.vhdl
new file mode 100644
index 000000000..108750cf1
--- /dev/null
+++ b/testsuite/synth/func01/func06.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity func06 is
+  port (s : natural;
+        r : out std_logic_vector (15 downto 0));
+end func06;
+
+architecture behav of func06 is
+  function mapv (sel : natural) return std_logic_vector
+  is
+    variable res : std_logic_vector(15 downto 0) := (others => '0');
+  begin
+    case sel is
+      when 2 =>
+        res := x"1234";
+      when 3 =>
+        res := x"5678";
+      when others =>
+        null;
+    end case;
+    return res;
+  end mapv; 
+begin
+  r <= mapv (s);
+end behav;
+    
diff --git a/testsuite/synth/func01/tb_func01.vhdl b/testsuite/synth/func01/tb_func01.vhdl
new file mode 100644
index 000000000..ec556c6f0
--- /dev/null
+++ b/testsuite/synth/func01/tb_func01.vhdl
@@ -0,0 +1,27 @@
+entity tb_func01 is
+end tb_func01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func01 is
+  signal a, b : std_logic_vector(7 downto 0);
+  signal sel : std_logic;
+begin
+  dut: entity work.func01
+    port map (a, sel, b);
+
+  process
+  begin
+    a <= x"5d";
+    sel <= '1';
+    wait for 1 ns;
+    assert b = x"0d" severity failure;
+
+    sel <= '0';
+    wait for 1 ns;
+    assert b = x"5d" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/tb_func02.vhdl b/testsuite/synth/func01/tb_func02.vhdl
new file mode 100644
index 000000000..c00db3a3a
--- /dev/null
+++ b/testsuite/synth/func01/tb_func02.vhdl
@@ -0,0 +1,29 @@
+entity tb_func02 is
+end tb_func02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func02 is
+  signal a, b : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.func02
+    port map (a, b);
+
+  process
+  begin
+    a <= x"5d";
+    wait for 1 ns;
+    assert b = x"01" severity failure;
+
+    a <= x"ff";
+    wait for 1 ns;
+    assert b = x"01" severity failure;
+
+    a <= x"fe";
+    wait for 1 ns;
+    assert b = x"00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/tb_func04.vhdl b/testsuite/synth/func01/tb_func04.vhdl
new file mode 100644
index 000000000..026afcaa5
--- /dev/null
+++ b/testsuite/synth/func01/tb_func04.vhdl
@@ -0,0 +1,27 @@
+entity tb_func04 is
+end tb_func04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func04 is
+  signal a, b, r : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.func04
+    port map (a, b, r);
+
+  process
+  begin
+    a <= x"5d";
+    b <= x"78";
+    wait for 1 ns;
+    assert r = x"79" severity failure;
+
+    a <= x"0f";
+    b <= x"f0";
+    wait for 1 ns;
+    assert r = x"f3" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/tb_func05.vhdl b/testsuite/synth/func01/tb_func05.vhdl
new file mode 100644
index 000000000..8f2e11704
--- /dev/null
+++ b/testsuite/synth/func01/tb_func05.vhdl
@@ -0,0 +1,26 @@
+entity tb_func05 is
+end tb_func05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func05 is
+  signal r : std_logic_vector(15 downto 0);
+  signal s : natural;
+begin
+  dut: entity work.func05
+    port map (s, r);
+
+  process
+  begin
+    s <= 2;
+    wait for 1 ns;
+    assert r = x"1234" severity failure;
+
+    s <= 3;
+    wait for 1 ns;
+    assert r = x"0000" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/tb_func06.vhdl b/testsuite/synth/func01/tb_func06.vhdl
new file mode 100644
index 000000000..17d09e55e
--- /dev/null
+++ b/testsuite/synth/func01/tb_func06.vhdl
@@ -0,0 +1,34 @@
+entity tb_func06 is
+end tb_func06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func06 is
+  signal r : std_logic_vector(15 downto 0);
+  signal s : natural;
+begin
+  dut: entity work.func06
+    port map (s, r);
+
+  process
+  begin
+    s <= 2;
+    wait for 1 ns;
+    assert r = x"1234" severity failure;
+
+    s <= 0;
+    wait for 1 ns;
+    assert r = x"0000" severity failure;
+
+    s <= 3;
+    wait for 1 ns;
+    assert r = x"5678" severity failure;
+
+    s <= 4;
+    wait for 1 ns;
+    assert r = x"0000" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/testsuite.sh b/testsuite/synth/func01/testsuite.sh
index e947b0e10..b08487cc4 100755
--- a/testsuite/synth/func01/testsuite.sh
+++ b/testsuite/synth/func01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in func03; do
+for t in func01 func02 func03 func04 func05 func06; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean