testsuite/synth: add fsm02 test.

5 files changed, 181 insertions, 0 deletions

diff --git a/testsuite/synth/fsm02/recv.sby b/testsuite/synth/fsm02/recv.sby
new file mode 100644
index 000000000..a9926a99b
--- /dev/null
+++ b/testsuite/synth/fsm02/recv.sby
@@ -0,0 +1,14 @@
+[options]
+mode bmc
+depth 100
+
+[engines]
+smtbmc
+
+[script]
+plugin -i ghdl
+ghdl -fpsl recv.vhdl -e recv
+prep -top recv
+
+[files]
+recv.vhdl
diff --git a/testsuite/synth/fsm02/recv.vhdl b/testsuite/synth/fsm02/recv.vhdl
new file mode 100644
index 000000000..11bbb152a
--- /dev/null
+++ b/testsuite/synth/fsm02/recv.vhdl
@@ -0,0 +1,94 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity recv is
+  port (
+    rst : std_logic;
+    clk : std_logic;
+    rx : std_logic;
+    byte : out std_logic_vector (7 downto 0);
+    b_err : out std_logic;
+    b_en : out std_logic);
+end recv;
+
+architecture behav of recv
+is
+    type state_t is
+         (s_wait, s0, s1, s2, s3, s4, s5, s6, s7, s_parity, s_stop);
+    signal state: state_t;
+    signal parity: std_logic;
+    signal err : std_logic;
+    signal en : std_logic;
+begin
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        state <= s_wait;
+        err <= '0';
+        en <= '0';
+      else
+        en <= '0';
+        case state is
+          when s_wait =>
+            if rx = '0' then
+              state <= s0;
+              err <= '0';
+              parity <= '0';
+            end if;
+          when s0 =>
+            byte (0) <= rx;
+            parity <= parity xor rx;
+            state <= s1;
+          when s1 =>
+            byte (1) <= rx;
+            parity <= parity xor rx;
+            state <= s2;
+          when s2 =>
+            byte (2) <= rx;
+            parity <= parity xor rx;
+            state <= s3;
+          when s3 =>
+            byte (3) <= rx;
+            parity <= parity xor rx;
+            state <= s4;
+          when s4 =>
+            byte (4) <= rx;
+            parity <= parity xor rx;
+            state <= s5;
+          when s5 =>
+            byte (5) <= rx;
+            parity <= parity xor rx;
+            state <= s6;
+          when s6 =>
+            byte (6) <= rx;
+            parity <= parity xor rx;
+            state <= s7;
+          when s7 =>
+            byte (7) <= rx;
+            parity <= parity xor rx;
+            state <= s_parity;
+          when s_parity =>
+            if rx /= parity then
+              err <= '1';
+            end if;
+            state <= s_stop;
+          when s_stop =>
+            if rx /= '1' then
+              err <= '1';
+            end if;
+            en <= '1';
+            state <= s_wait;
+        end case;
+      end if;
+    end if;
+  end process;
+
+    b_en <= en;
+    b_err <= err;
+
+    --psl default clock is rising_edge(clk);
+    --psl restrict {rst;(not rst)[*]};
+
+    assert rst = '1' or err /= '1' report "parity error" severity error;
+end behav;
diff --git a/testsuite/synth/fsm02/tb_recv.ghw b/testsuite/synth/fsm02/tb_recv.ghw
new file mode 100644
index 000000000..f668b2ab7
--- /dev/null
+++ b/testsuite/synth/fsm02/tb_recv.ghw
diff --git a/testsuite/synth/fsm02/tb_recv.vhdl b/testsuite/synth/fsm02/tb_recv.vhdl
new file mode 100644
index 000000000..d6f0bb048
--- /dev/null
+++ b/testsuite/synth/fsm02/tb_recv.vhdl
@@ -0,0 +1,57 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_recv is
+end tb_recv;
+
+architecture behav of tb_recv is
+    signal clk : std_logic;
+    signal rst : std_logic := '1';
+    signal tx : std_logic;
+    signal data : std_logic_vector (7 downto 0);
+    signal valid : std_logic;
+    signal err : std_logic;
+begin
+    dut: entity work.recv
+      port map (clk => clk,
+        rst => rst,
+        rx => tx,
+        byte => data,
+        b_err => err,
+        b_en => valid);
+    
+    process
+        procedure pulse is
+        begin
+            clk <= '0';
+            wait for 1 ns;
+            clk <= '1';
+            wait for 1 ns;
+        end pulse;
+        variable txdata : std_logic_vector (7 downto 0);
+    begin
+        rst <= '1';
+        tx <= '1';
+        pulse;
+        rst <= '0';
+        
+        --  Transmit 1 byte.
+        tx <= '0';
+        pulse;
+        assert err = '0' and valid = '0' severity error;
+        txdata := x"6e";
+        for i in txdata'reverse_range loop
+            tx <= txdata(i);
+            pulse;
+            assert err = '0' and valid = '0' severity error;
+        end loop;
+        tx <= '1';  -- parity
+        pulse;
+        tx <= '1';  --  stop
+        pulse;
+        assert valid = '1' severity error;
+        assert err = '0' severity error;
+        assert data = txdata;
+        wait;
+    end process;
+end behav;
\ No newline at end of file
diff --git a/testsuite/synth/fsm02/testsuite.sh b/testsuite/synth/fsm02/testsuite.sh
new file mode 100755
index 000000000..6326874de
--- /dev/null
+++ b/testsuite/synth/fsm02/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in recv; do
+    analyze -fpsl $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth -fpsl $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"