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author | Tristan Gingold <tgingold@free.fr> | 2019-11-01 18:46:16 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-01 18:46:16 +0100 |
commit | 66b34c936b1ef472a532673bed0543287311e995 (patch) | |
tree | 37b82cb3ba3ae9238bbb8c52990f360a69a8c936 /testsuite/synth/forgen01/tb_forgen03.vhdl | |
parent | a4b5dd0fb373bf785abfc1f6666ce8d6a32a6e08 (diff) | |
download | ghdl-66b34c936b1ef472a532673bed0543287311e995.tar.gz ghdl-66b34c936b1ef472a532673bed0543287311e995.tar.bz2 ghdl-66b34c936b1ef472a532673bed0543287311e995.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/forgen01/tb_forgen03.vhdl')
-rw-r--r-- | testsuite/synth/forgen01/tb_forgen03.vhdl | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/forgen01/tb_forgen03.vhdl b/testsuite/synth/forgen01/tb_forgen03.vhdl new file mode 100644 index 000000000..d03046781 --- /dev/null +++ b/testsuite/synth/forgen01/tb_forgen03.vhdl @@ -0,0 +1,29 @@ +entity tb_forgen03 is +end tb_forgen03; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_forgen03 is + signal a : std_logic_vector (7 downto 0); + signal b : std_logic_vector (7 downto 0); + signal o : std_logic_vector (7 downto 0); +begin + dut: entity work.forgen03 + port map (a, b, o); + + process + begin + a <= x"30"; + b <= x"28"; + wait for 1 ns; + assert o = x"58" severity failure; + + a <= x"11"; + b <= x"f7"; + wait for 1 ns; + assert o = x"08" severity failure; + + wait; + end process; +end behav; |