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author | Tristan Gingold <tgingold@free.fr> | 2019-07-20 18:52:06 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-20 18:52:06 +0200 |
commit | 7bafc11a48a61526093ce2ce31fc5d91bd1a4a0f (patch) | |
tree | fe28a40089a6513cffd2be65ded71dee1a27621e /testsuite/synth/forgen01/forgen01.vhdl | |
parent | fb10c9a037972b4bea76f8b4af98e97498978531 (diff) | |
download | ghdl-7bafc11a48a61526093ce2ce31fc5d91bd1a4a0f.tar.gz ghdl-7bafc11a48a61526093ce2ce31fc5d91bd1a4a0f.tar.bz2 ghdl-7bafc11a48a61526093ce2ce31fc5d91bd1a4a0f.zip |
synth: fix test name.
Diffstat (limited to 'testsuite/synth/forgen01/forgen01.vhdl')
-rw-r--r-- | testsuite/synth/forgen01/forgen01.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/synth/forgen01/forgen01.vhdl b/testsuite/synth/forgen01/forgen01.vhdl new file mode 100644 index 000000000..b3e5a0eb0 --- /dev/null +++ b/testsuite/synth/forgen01/forgen01.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity forgen01 is + port (a : out std_logic_vector (7 downto 0)); +end; + +architecture behav of forgen01 is + constant c : std_logic_vector (7 downto 0) := x"a1"; +begin + gen: for i in a'range generate + a (i) <= c (i); + end generate; +end behav; |