synth: fix test name.

1 files changed, 14 insertions, 0 deletions

diff --git a/testsuite/synth/forgen01/forgen01.vhdl b/testsuite/synth/forgen01/forgen01.vhdl
new file mode 100644
index 000000000..b3e5a0eb0
--- /dev/null
+++ b/testsuite/synth/forgen01/forgen01.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity forgen01 is
+  port (a : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of forgen01 is
+  constant c : std_logic_vector (7 downto 0) := x"a1";
+begin
+  gen: for i in a'range generate
+    a (i) <= c (i);
+  end generate;
+end behav;