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author | Tristan Gingold <tgingold@free.fr> | 2023-04-23 19:30:38 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-04-23 19:30:38 +0200 |
commit | b650e63e2495ad97a850af9c7ba8978dbfbd3100 (patch) | |
tree | 8456f29e66c3a0fc21632287830256eca1fe2a4b /testsuite/synth/external01 | |
parent | 0ffb1ee5a504c47eb447ebc313a8f8fc6dc74806 (diff) | |
download | ghdl-b650e63e2495ad97a850af9c7ba8978dbfbd3100.tar.gz ghdl-b650e63e2495ad97a850af9c7ba8978dbfbd3100.tar.bz2 ghdl-b650e63e2495ad97a850af9c7ba8978dbfbd3100.zip |
testsuite/synth: add a test for external names with components
Diffstat (limited to 'testsuite/synth/external01')
-rw-r--r-- | testsuite/synth/external01/external02.vhdl | 65 | ||||
-rwxr-xr-x | testsuite/synth/external01/testsuite.sh | 1 |
2 files changed, 66 insertions, 0 deletions
diff --git a/testsuite/synth/external01/external02.vhdl b/testsuite/synth/external01/external02.vhdl new file mode 100644 index 000000000..5cab0d980 --- /dev/null +++ b/testsuite/synth/external01/external02.vhdl @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity external02_sub is + port (clk : std_logic; + rst : std_logic; + a : std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0)); +end external02_sub; + +architecture behav of external02_sub is + signal accum : std_logic_vector(7 downto 0); +begin + process (clk) is + begin + if rising_edge(clk) then + if rst = '1' then + accum <= (others => '0'); + else + accum <= std_logic_vector(unsigned(accum) + unsigned(a)); + end if; + end if; + end process; + + process (clk) is + begin + if rising_edge(clk) then + if rst = '1' then + o <= (others => '0'); + else + o <= accum; + end if; + end if; + end process; +end behav; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity external02 is + port (clk : std_logic; + rst : std_logic; + a : std_logic_vector(7 downto 0); + accum : out std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0)); +end external02; + +architecture behav of external02 is + component external02_sub is + port ( + clk : std_logic; + rst : std_logic; + a : std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0)); + end component external02_sub; +begin + dut : external02_sub + port map (clk => clk, + rst => rst, + a => a, + o => o); + accum <= << signal .external02.dut.accum : std_logic_vector(7 downto 0) >>; +end behav; diff --git a/testsuite/synth/external01/testsuite.sh b/testsuite/synth/external01/testsuite.sh index 12ca0c07a..b21120cdc 100755 --- a/testsuite/synth/external01/testsuite.sh +++ b/testsuite/synth/external01/testsuite.sh @@ -6,6 +6,7 @@ GHDL_STD_FLAGS=--std=08 GHDL_SYNTH_FLAGS=--keep-hierarchy=no synth_only external01 +synth_only external02 synth_failure externalerr01.vhdl -e synth_failure externalerr02.vhdl -e |