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author | Tristan Gingold <tgingold@free.fr> | 2019-10-08 18:43:52 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-08 18:43:52 +0200 |
commit | 0a3ca95575c7c5d3c153ec2de271613c228124a8 (patch) | |
tree | 43234189433a515b75591e9ce814236cd633a09e /testsuite/synth/dispout01/rec10.vhdl | |
parent | 32272b4c7e384e0f54a8216ee14db5b8554f9793 (diff) | |
download | ghdl-0a3ca95575c7c5d3c153ec2de271613c228124a8.tar.gz ghdl-0a3ca95575c7c5d3c153ec2de271613c228124a8.tar.bz2 ghdl-0a3ca95575c7c5d3c153ec2de271613c228124a8.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/dispout01/rec10.vhdl')
-rw-r--r-- | testsuite/synth/dispout01/rec10.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/dispout01/rec10.vhdl b/testsuite/synth/dispout01/rec10.vhdl new file mode 100644 index 000000000..2e53bac22 --- /dev/null +++ b/testsuite/synth/dispout01/rec10.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.rec10_pkg.all; + +entity rec10 is + port (inp : std_logic; + o : out myrec); +end rec10; + +architecture behav of rec10 is +begin + o.b (1) <= not inp; +end behav; |