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authorTristan Gingold <tgingold@free.fr>2019-10-08 18:43:52 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-08 18:43:52 +0200
commit0a3ca95575c7c5d3c153ec2de271613c228124a8 (patch)
tree43234189433a515b75591e9ce814236cd633a09e /testsuite/synth/dispout01/rec10.vhdl
parent32272b4c7e384e0f54a8216ee14db5b8554f9793 (diff)
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testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/dispout01/rec10.vhdl')
-rw-r--r--testsuite/synth/dispout01/rec10.vhdl13
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diff --git a/testsuite/synth/dispout01/rec10.vhdl b/testsuite/synth/dispout01/rec10.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec10_pkg.all;
+
+entity rec10 is
+ port (inp : std_logic;
+ o : out myrec);
+end rec10;
+
+architecture behav of rec10 is
+begin
+ o.b (1) <= not inp;
+end behav;