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authorTristan Gingold <tgingold@free.fr>2019-09-04 06:52:35 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-04 06:52:35 +0200
commit4cb565baea6e93f804bef253200f0872428a3daa (patch)
tree6ed5ee76fe6c1c9e52d94a03666e1d121ccfd094 /testsuite/synth/dispin01/tb_rec04.vhdl
parent95433bc986b16badf5a48ab00df861d0424ca983 (diff)
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testsuite/synth: rename disp01 to dispin01
Diffstat (limited to 'testsuite/synth/dispin01/tb_rec04.vhdl')
-rw-r--r--testsuite/synth/dispin01/tb_rec04.vhdl39
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/dispin01/tb_rec04.vhdl b/testsuite/synth/dispin01/tb_rec04.vhdl
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+++ b/testsuite/synth/dispin01/tb_rec04.vhdl
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+entity tb_rec04 is
+end tb_rec04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec04_pkg.all;
+
+architecture behav of tb_rec04 is
+ signal inp : myrec;
+ signal r : std_logic;
+begin
+ dut: entity work.rec04
+ port map (inp => inp, o => r);
+
+ process
+ begin
+ inp.a <= "0000";
+ inp.b <= '1';
+ wait for 1 ns;
+ assert r = '0' severity failure;
+
+ inp.a <= "0010";
+ inp.b <= '1';
+ wait for 1 ns;
+ assert r = '1' severity failure;
+
+ inp.a <= "1101";
+ inp.b <= '0';
+ wait for 1 ns;
+ assert r = '1' severity failure;
+
+ inp.a <= "1101";
+ inp.b <= '1';
+ wait for 1 ns;
+ assert r = '0' severity failure;
+
+ wait;
+ end process;
+end behav;