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author | Tristan Gingold <tgingold@free.fr> | 2019-09-04 06:52:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-04 06:52:35 +0200 |
commit | 4cb565baea6e93f804bef253200f0872428a3daa (patch) | |
tree | 6ed5ee76fe6c1c9e52d94a03666e1d121ccfd094 /testsuite/synth/dispin01/pkg_rec01.vhdl | |
parent | 95433bc986b16badf5a48ab00df861d0424ca983 (diff) | |
download | ghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.gz ghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.bz2 ghdl-4cb565baea6e93f804bef253200f0872428a3daa.zip |
testsuite/synth: rename disp01 to dispin01
Diffstat (limited to 'testsuite/synth/dispin01/pkg_rec01.vhdl')
-rw-r--r-- | testsuite/synth/dispin01/pkg_rec01.vhdl | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/testsuite/synth/dispin01/pkg_rec01.vhdl b/testsuite/synth/dispin01/pkg_rec01.vhdl new file mode 100644 index 000000000..c2048c3ea --- /dev/null +++ b/testsuite/synth/dispin01/pkg_rec01.vhdl @@ -0,0 +1,9 @@ +library ieee; +use ieee.std_logic_1164.all; + +package rec01_pkg is + type myrec is record + a : std_logic; + b : std_logic; + end record; +end rec01_pkg; |