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author | Tristan Gingold <tgingold@free.fr> | 2019-06-29 11:37:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-06-29 11:37:35 +0200 |
commit | 4d71e55689449b49b6732e26a34469188564f8b4 (patch) | |
tree | 0e24456ef5086a1fea2945894a69cb0998209cfd /testsuite/synth/dff01/tb_dff03.vhdl | |
parent | 5fc2b23c0a27e281d3c1f1927379aa1fd9300df0 (diff) | |
download | ghdl-4d71e55689449b49b6732e26a34469188564f8b4.tar.gz ghdl-4d71e55689449b49b6732e26a34469188564f8b4.tar.bz2 ghdl-4d71e55689449b49b6732e26a34469188564f8b4.zip |
testsuite/synth/dff01: add testbenches.
Diffstat (limited to 'testsuite/synth/dff01/tb_dff03.vhdl')
-rw-r--r-- | testsuite/synth/dff01/tb_dff03.vhdl | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/testsuite/synth/dff01/tb_dff03.vhdl b/testsuite/synth/dff01/tb_dff03.vhdl new file mode 100644 index 000000000..97d60d684 --- /dev/null +++ b/testsuite/synth/dff01/tb_dff03.vhdl @@ -0,0 +1,40 @@ +entity tb_dff03 is +end tb_dff03; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_dff03 is + signal clk : std_logic; + signal din : std_logic_vector (7 downto 0); + signal dout : std_logic_vector (7 downto 0); +begin + dut: entity work.dff03 + port map ( + q => dout, + d => din, + clk => clk); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + din <= x"00"; + pulse; + assert dout = x"00" severity failure; + din <= x"ab"; + pulse; + assert dout = x"ab" severity failure; + pulse; + assert dout = x"ab" severity failure; + din <= x"12"; + pulse; + assert dout = x"12" severity failure; + wait; + end process; +end behav; |