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authorTristan Gingold <tgingold@free.fr>2020-05-07 07:53:24 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-07 07:53:24 +0200
commitb722b0f53ec0abceeda88bb65a0eaf7d0ba743b2 (patch)
treed4a956afc7cb1bf5d21c8b1630fbbe6ddec314fe /testsuite/synth/conv01
parent025ffd8038acb7aa8a1348799ff7d90cfeb579b9 (diff)
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testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/conv01')
-rw-r--r--testsuite/synth/conv01/pos01.vhdl48
-rwxr-xr-xtestsuite/synth/conv01/testsuite.sh2
2 files changed, 49 insertions, 1 deletions
diff --git a/testsuite/synth/conv01/pos01.vhdl b/testsuite/synth/conv01/pos01.vhdl
new file mode 100644
index 000000000..94b943a98
--- /dev/null
+++ b/testsuite/synth/conv01/pos01.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pos01 is
+ generic (g_en : boolean := True);
+ port (clk : std_logic;
+ rst : std_logic;
+ en : std_logic;
+ st : out std_logic_vector(1 downto 0));
+end pos01;
+
+architecture behav of pos01 is
+ type t_state is (IDLE, WAIT1, WAIT2, DONE);
+ signal s : t_state;
+ constant c1 : integer := t_state'pos(WAIT2);
+ constant c2 : integer := boolean'pos(g_en);
+begin
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ s <= IDLE;
+ else
+ case s is
+ when IDLE =>
+ if en = '1' then
+ s <= WAIT1;
+ end if;
+ when WAIT1 =>
+ if en = '1' then
+ s <= WAIT2;
+ end if;
+ when WAIT2 =>
+ if en = '1' then
+ s <= DONE;
+ end if;
+ when DONE =>
+ null;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ st <= std_logic_vector(to_unsigned(t_state'pos(s), 2));
+end behav;
+
+
diff --git a/testsuite/synth/conv01/testsuite.sh b/testsuite/synth/conv01/testsuite.sh
index 7de4702f2..aee0f6db9 100755
--- a/testsuite/synth/conv01/testsuite.sh
+++ b/testsuite/synth/conv01/testsuite.sh
@@ -2,7 +2,7 @@
. ../../testenv.sh
-for t in conv01; do
+for t in conv01 pos01; do
synth_analyze $t
clean
done