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authorTristan Gingold <tgingold@free.fr>2022-04-29 05:03:57 +0200
committerTristan Gingold <tgingold@free.fr>2022-04-29 05:03:57 +0200
commit5013d867c156c35d28ecaffd840e80e25d64c119 (patch)
tree03c5837dffae7dd29c234902916a07499d813a8a /testsuite/synth/comp04/comp04.vhdl
parent4433b25c12938ddd2d3a673148fe7a7aee844fb3 (diff)
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testsuite/synth: add more tests for component
Diffstat (limited to 'testsuite/synth/comp04/comp04.vhdl')
-rw-r--r--testsuite/synth/comp04/comp04.vhdl43
1 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/synth/comp04/comp04.vhdl b/testsuite/synth/comp04/comp04.vhdl
new file mode 100644
index 000000000..af208cf44
--- /dev/null
+++ b/testsuite/synth/comp04/comp04.vhdl
@@ -0,0 +1,43 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mand is
+ port (v : std_logic_vector (7 downto 0);
+ b : std_logic;
+ r : out std_logic_vector (7 downto 0));
+end mand;
+
+architecture behav of mand is
+begin
+ process (v, b)
+ begin
+ for i in v'range loop
+ r(i) <= v (i) and b;
+ end loop;
+ end process;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comp04 is
+ port (v : std_logic_vector (7 downto 0);
+ r : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of comp04 is
+ component mand is
+ port (
+ b : std_logic;
+ v : std_logic_vector (7 downto 0);
+ r : out std_logic_vector (7 downto 0));
+ end component;
+
+begin
+ dut : mand
+ port map (v => v,
+ b => v(0),
+ r => r);
+end behav;
+
+