synth: add test for previous commit.

3 files changed, 77 insertions, 2 deletions

diff --git a/testsuite/synth/cnt01/cnt02.vhdl b/testsuite/synth/cnt01/cnt02.vhdl
new file mode 100644
index 000000000..0a2d35ede
--- /dev/null
+++ b/testsuite/synth/cnt01/cnt02.vhdl
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity cnt02 is
+  port (
+    clk       : in STD_LOGIC;
+    rst       : in STD_LOGIC;
+
+    low : out std_logic
+    );
+end cnt02;
+
+architecture behav of cnt02 is
+  signal counter : integer range 0 to 63;
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        counter <= 63;
+      else
+        counter <= counter - 1;
+      end if;
+    end if;
+  end process;
+
+  low <= '1' when counter < 60 else '0';
+end behav;
diff --git a/testsuite/synth/cnt01/tb_cnt02.vhdl b/testsuite/synth/cnt01/tb_cnt02.vhdl
new file mode 100644
index 000000000..b7abd8c90
--- /dev/null
+++ b/testsuite/synth/cnt01/tb_cnt02.vhdl
@@ -0,0 +1,46 @@
+entity tb_cnt02 is
+end tb_cnt02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_cnt02 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal low : std_logic;
+begin
+  dut: entity work.cnt02
+    port map (clk => clk, rst => rst, low => low);
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    pulse;
+    assert low = '0' severity failure;
+
+    rst <= '0';
+    pulse;
+    assert low = '0' severity failure;
+
+    pulse;
+    assert low = '0' severity failure;
+
+    pulse;
+    assert low = '0' severity failure;
+
+    pulse;
+    assert low = '1' severity failure;
+
+    pulse;
+    assert low = '1' severity failure;
+
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/cnt01/testsuite.sh b/testsuite/synth/cnt01/testsuite.sh
index e791a3dcb..f01df2cc7 100755
--- a/testsuite/synth/cnt01/testsuite.sh
+++ b/testsuite/synth/cnt01/testsuite.sh
@@ -2,14 +2,14 @@
 
 . ../../testenv.sh
 
-for t in cnt01; do
+for t in cnt01 cnt02; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
 
     synth $t.vhdl -e $t > syn_$t.vhdl
     analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
     clean
 done