testsuite/synth: add testcase for previous commit.

3 files changed, 51 insertions, 1 deletions

diff --git a/testsuite/synth/case02/case02.vhdl b/testsuite/synth/case02/case02.vhdl
new file mode 100644
index 000000000..6dba9d594
--- /dev/null
+++ b/testsuite/synth/case02/case02.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case02 is
+  port (a : std_logic_vector (1 downto 0);
+        o : out std_logic);
+end case02;
+
+architecture behav of case02 is
+begin
+  process (a)
+  begin
+    case a(1 downto 0) is
+      when "01" =>
+        o <= '1';
+      when others =>
+        o <= '0';
+    end case;
+  end process;
+end behav;
diff --git a/testsuite/synth/case02/tb_case02.vhdl b/testsuite/synth/case02/tb_case02.vhdl
new file mode 100644
index 000000000..ae23a2276
--- /dev/null
+++ b/testsuite/synth/case02/tb_case02.vhdl
@@ -0,0 +1,30 @@
+entity tb_case02 is
+end tb_case02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_case02 is
+  signal a : std_logic_vector (1 downto 0);
+  signal o : std_logic;
+begin
+  dut: entity work.case02
+    port map (a, o);
+
+  process
+  begin
+    a <= "00";
+    wait for 1 ns;
+    assert o = '0';
+
+    a <= "01";
+    wait for 1 ns;
+    assert o = '1';
+
+    a <= "10";
+    wait for 1 ns;
+    assert o = '0';
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/case02/testsuite.sh b/testsuite/synth/case02/testsuite.sh
index fe81cddf9..ecb19a503 100755
--- a/testsuite/synth/case02/testsuite.sh
+++ b/testsuite/synth/case02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in case01; do
+for t in case01 case02; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean