testsuite/synth: add case tests for corner case.

5 files changed, 85 insertions, 9 deletions

diff --git a/testsuite/synth/case01/case03.vhdl b/testsuite/synth/case01/case03.vhdl
new file mode 100644
index 000000000..3f1894afa
--- /dev/null
+++ b/testsuite/synth/case01/case03.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case03 is
+  port (a : std_logic_vector (4 downto 0);
+        o : out std_logic);
+end case03;
+
+architecture behav of case03 is
+begin
+  with a select o <=
+    '0' when others;
+end behav;
diff --git a/testsuite/synth/case01/case04.vhdl b/testsuite/synth/case01/case04.vhdl
new file mode 100644
index 000000000..cf90e85ed
--- /dev/null
+++ b/testsuite/synth/case01/case04.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case04 is
+  port (a : std_logic_vector (4 downto 0);
+        o : out std_logic);
+end case04;
+
+architecture behav of case04 is
+begin
+  process (a)
+  begin
+    o <= '0';
+    case a is
+      when others =>
+        o <= '1';
+    end case;
+  end process;
+end behav;
diff --git a/testsuite/synth/case01/tb_case03.vhdl b/testsuite/synth/case01/tb_case03.vhdl
new file mode 100644
index 000000000..7706b77c5
--- /dev/null
+++ b/testsuite/synth/case01/tb_case03.vhdl
@@ -0,0 +1,27 @@
+entity tb_case03 is
+end tb_case03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_case03 is
+  signal s : std_logic_vector (4 downto 0);
+  signal o : std_logic;
+begin
+  dut: entity work.case03
+    port map (s, o);
+
+  process
+  begin
+    s <= "10011";
+    wait for 1 ns;
+    assert o = '0' severity failure;
+
+    s <= "00000";
+    wait for 1 ns;
+    assert o = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/case01/tb_case04.vhdl b/testsuite/synth/case01/tb_case04.vhdl
new file mode 100644
index 000000000..ea3b6b5e6
--- /dev/null
+++ b/testsuite/synth/case01/tb_case04.vhdl
@@ -0,0 +1,24 @@
+entity tb_case04 is
+end tb_case04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_case04 is
+  signal s : std_logic_vector (4 downto 0);
+  signal o : std_logic;
+begin
+  dut: entity work.case04
+    port map (s, o);
+
+  process
+  begin
+    s <= "00010";
+    wait for 1 ns;
+
+    assert o = '1' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/case01/testsuite.sh b/testsuite/synth/case01/testsuite.sh
index ecb19a503..8ff30eaf1 100755
--- a/testsuite/synth/case01/testsuite.sh
+++ b/testsuite/synth/case01/testsuite.sh
@@ -2,15 +2,8 @@
 
 . ../../testenv.sh
 
-for t in case01 case02; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
+for t in case01 case02 case03 case04; do
+    synth_tb $t
 done
 
 echo "Test successful"