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author | Tristan Gingold <tgingold@free.fr> | 2019-07-24 08:30:07 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-24 08:30:07 +0200 |
commit | a458b0b9bde7d3152adf9b78c5d0a56c5d45915f (patch) | |
tree | 6d0a7ad590764a559ea70a389ffccb8f5d8d08c3 /testsuite/synth/case01/tb_case02.vhdl | |
parent | 121b6579b633d814e27980e1c48c46582276885e (diff) | |
download | ghdl-a458b0b9bde7d3152adf9b78c5d0a56c5d45915f.tar.gz ghdl-a458b0b9bde7d3152adf9b78c5d0a56c5d45915f.tar.bz2 ghdl-a458b0b9bde7d3152adf9b78c5d0a56c5d45915f.zip |
synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/case01/tb_case02.vhdl')
-rw-r--r-- | testsuite/synth/case01/tb_case02.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/case01/tb_case02.vhdl b/testsuite/synth/case01/tb_case02.vhdl new file mode 100644 index 000000000..06b4b0789 --- /dev/null +++ b/testsuite/synth/case01/tb_case02.vhdl @@ -0,0 +1,26 @@ +entity tb_case02 is +end tb_case02; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_case02 is + signal s : std_logic_vector (4 downto 0); + signal o : std_logic; +begin + dut: entity work.case02 + port map (s, o); + + process + constant ov : std_logic_vector (0 to 31) := + b"00010011000010001100000000000000"; + begin + for i in ov'range loop + s <= std_logic_vector(to_unsigned(i, 5)); + wait for 1 ns; + assert o = ov(i) severity failure; + end loop; + wait; + end process; +end behav; |