testsuite/synth: add a test for previous commit.

3 files changed, 61 insertions, 9 deletions

diff --git a/testsuite/synth/asgn01/asgn09.vhdl b/testsuite/synth/asgn01/asgn09.vhdl
new file mode 100644
index 000000000..3a947ecc1
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn09.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn09 is
+  port (a, b, c, d : std_logic_vector (1 downto 0);
+        sel : std_logic_vector(1 downto 0);
+        o : out std_logic_vector (3 downto 0));
+end asgn09;
+
+architecture behav of asgn09 is
+begin
+  with sel select
+    o (1 downto 0) <= a when "00",
+    b when "01",
+    c when "10",
+    d when others;
+  o(3 downto 2) <= a or b;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_asgn09.vhdl b/testsuite/synth/asgn01/tb_asgn09.vhdl
new file mode 100644
index 000000000..156e50666
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn09.vhdl
@@ -0,0 +1,40 @@
+entity tb_asgn09 is
+end tb_asgn09;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn09 is
+  signal a, b, c, d : std_logic_vector (1 downto 0);
+  signal sel        : std_logic_vector(1 downto 0);
+  signal o          : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.asgn09
+    port map (a, b, c, d, sel, o);
+
+  process
+  begin
+    a <= "10";
+    b <= "01";
+    c <= "00";
+    d <= "11";
+
+    sel <= "00";
+    wait for 1 ns;
+    assert o = "1110" severity failure;
+
+    sel <= "01";
+    wait for 1 ns;
+    assert o = "1101" severity failure;
+
+    sel <= "10";
+    wait for 1 ns;
+    assert o = "1100" severity failure;
+
+    sel <= "11";
+    wait for 1 ns;
+    assert o = "1111" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/testsuite.sh b/testsuite/synth/asgn01/testsuite.sh
index ad298ced7..dc82fd270 100755
--- a/testsuite/synth/asgn01/testsuite.sh
+++ b/testsuite/synth/asgn01/testsuite.sh
@@ -2,15 +2,9 @@
 
 . ../../testenv.sh
 
-for t in asgn01 asgn02 asgn03 asgn04 asgn05 asgn06 asgn07 asgn08 arr04; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
+for t in asgn01 asgn02 asgn03 asgn04 asgn05 asgn06 asgn07 asgn08 \
+	 arr04 asgn09; do
+    synth_tb $t
 done
 
 echo "Test successful"