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authorTristan Gingold <tgingold@free.fr>2019-10-01 20:03:56 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-01 20:03:56 +0200
commit08b709a5419c49bca150db52a93167f4a1685f26 (patch)
tree95bc8087bb82f9b1a41feae9ff347993138f6830 /testsuite/synth/asgn01
parent6324fe8dc6aba1e0a57575a2986407df150f59f3 (diff)
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testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/asgn01')
-rw-r--r--testsuite/synth/asgn01/asgn06.vhdl26
-rw-r--r--testsuite/synth/asgn01/tb_asgn06.vhdl38
-rwxr-xr-xtestsuite/synth/asgn01/testsuite.sh2
3 files changed, 65 insertions, 1 deletions
diff --git a/testsuite/synth/asgn01/asgn06.vhdl b/testsuite/synth/asgn01/asgn06.vhdl
new file mode 100644
index 000000000..475f632be
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn06.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn06 is
+ port (clk : std_logic;
+ s0 : std_logic;
+ r : out std_logic_vector (65 downto 0));
+end asgn06;
+
+architecture behav of asgn06 is
+begin
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if s0 = '1' then
+ r (0) <= '0';
+ r (8 downto 5) <= x"9";
+ r (65) <= '0';
+ else
+ r (0) <= '1';
+ r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
+ r (65) <= '1';
+ end if;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_asgn06.vhdl b/testsuite/synth/asgn01/tb_asgn06.vhdl
new file mode 100644
index 000000000..82870f465
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn06.vhdl
@@ -0,0 +1,38 @@
+entity tb_asgn06 is
+end tb_asgn06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn06 is
+ signal s0 : std_logic;
+ signal clk : std_logic;
+ signal r : std_logic_vector (65 downto 0);
+begin
+ dut: entity work.asgn06
+ port map (clk => clk, s0 => s0, r => r);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ s0 <= '0';
+ pulse;
+ assert r (0) = '1' severity failure;
+ assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
+ assert r (65) = '1' severity failure;
+
+ s0 <= '1';
+ pulse;
+ assert r (0) = '0' severity failure;
+ assert r (64 downto 1) = x"ffff_eeee_dddd_cc9c" severity failure;
+ assert r (65) = '0' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/asgn01/testsuite.sh b/testsuite/synth/asgn01/testsuite.sh
index c42e9c0f1..f9991f800 100755
--- a/testsuite/synth/asgn01/testsuite.sh
+++ b/testsuite/synth/asgn01/testsuite.sh
@@ -2,7 +2,7 @@
. ../../testenv.sh
-for t in asgn01 asgn02 asgn03 asgn04 asgn05 arr04; do
+for t in asgn01 asgn02 asgn03 asgn04 asgn05 asgn06 arr04; do
analyze $t.vhdl tb_$t.vhdl
elab_simulate tb_$t
clean