testsuite/synth: add testcase for previous commit.

3 files changed, 46 insertions, 1 deletions

diff --git a/testsuite/synth/arr01/arr09.vhdl b/testsuite/synth/arr01/arr09.vhdl
new file mode 100644
index 000000000..37692f472
--- /dev/null
+++ b/testsuite/synth/arr01/arr09.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity arr09 is
+  port (val : std_logic_vector(3 downto 0);
+        res : out character);
+end arr09;
+
+architecture behav of arr09 is
+  type map_type is array (natural range 0 to 15) of character;
+  constant cmap : map_type := "0123456789abcdef";
+
+  function convert (v : natural range 0 to 15) return character
+  is
+    variable r : character;
+  begin
+    r := cmap (v);
+    return r;
+  end convert;
+begin
+  res <= convert (3);
+end behav;
diff --git a/testsuite/synth/arr01/tb_arr09.vhdl b/testsuite/synth/arr01/tb_arr09.vhdl
new file mode 100644
index 000000000..ce864099d
--- /dev/null
+++ b/testsuite/synth/arr01/tb_arr09.vhdl
@@ -0,0 +1,22 @@
+entity tb_arr09 is
+end tb_arr09;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_arr09 is
+  signal val : std_logic_vector(3 downto 0);
+  signal res : character;
+begin
+  dut: entity work.arr09
+    port map (val => val, res => res);
+
+  process
+  begin
+    wait for 1 ns;
+    assert res = '3' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr01/testsuite.sh b/testsuite/synth/arr01/testsuite.sh
index 71b198348..f6fd4ba56 100755
--- a/testsuite/synth/arr01/testsuite.sh
+++ b/testsuite/synth/arr01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in arr01 arr02 arr04 arr05 arr06 arr07; do
+for t in arr01 arr02 arr04 arr05 arr06 arr07 arr09; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean