testsuite/synth: add a test for previous commit

3 files changed, 82 insertions, 1 deletions

diff --git a/testsuite/synth/aggr02/targ03.vhdl b/testsuite/synth/aggr02/targ03.vhdl
new file mode 100644
index 000000000..7870da8d6
--- /dev/null
+++ b/testsuite/synth/aggr02/targ03.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity targ03 is
+  port (rdat : out std_logic_vector (7 downto 0);
+        rv : out std_logic;
+        wdat : std_logic_vector (7 downto 0);
+        wval : std_logic;
+        wen : std_logic;
+        clk : std_logic);
+end targ03;
+
+architecture behav of targ03 is
+  type memdat is record
+    d1 : std_logic_vector(7 downto 0);
+    v : std_logic;
+  end record;
+begin
+  process (clk)
+    variable m : memdat;
+  begin
+    if rising_edge (clk) then
+      if wen = '1' then
+        m := (wdat, wval);
+      end if;
+      (rdat, rv) <= m;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/aggr02/tb_targ03.vhdl b/testsuite/synth/aggr02/tb_targ03.vhdl
new file mode 100644
index 000000000..59a1b6a04
--- /dev/null
+++ b/testsuite/synth/aggr02/tb_targ03.vhdl
@@ -0,0 +1,51 @@
+entity tb_targ03 is
+end tb_targ03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_targ03 is
+  signal rdat : std_logic_vector (7 downto 0);
+  signal rv   : std_logic;
+  signal wdat : std_logic_vector (7 downto 0);
+  signal wval : std_logic;
+  signal wen  : std_logic;
+  signal clk  : std_logic;
+begin
+  dut: entity work.targ03
+    port map (rdat => rdat, rv => rv,
+              wdat => wdat, wval => wval,
+              wen => wen, clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wen <= '1';
+    wdat <= x"45";
+    wval <= '1';
+    pulse;
+    assert rdat = x"45" severity failure;
+    assert rv = '1' severity failure;
+
+    wdat <= x"ca";
+    wval <= '0';
+    pulse;
+    assert rdat = x"ca" severity failure;
+    assert rv = '0' severity failure;
+
+    wen <= '0';
+    wdat <= x"e3";
+    wval <= '1';
+    pulse;
+    assert rdat = x"ca" severity failure;
+    assert rv = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/aggr02/testsuite.sh b/testsuite/synth/aggr02/testsuite.sh
index 6c7deeb40..dfe5683b8 100755
--- a/testsuite/synth/aggr02/testsuite.sh
+++ b/testsuite/synth/aggr02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in targ01 targ02; do
+for t in targ01 targ02 targ03; do
     synth_tb $t
 done