synth: add testcase for aggregate target.

3 files changed, 56 insertions, 0 deletions

diff --git a/testsuite/synth/aggr02/targ01.vhdl b/testsuite/synth/aggr02/targ01.vhdl
new file mode 100644
index 000000000..f794fc8dc
--- /dev/null
+++ b/testsuite/synth/aggr02/targ01.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity targ01 is
+  port (v : std_logic_vector (2 downto 0);
+        o0, o1, o2 : out std_logic);
+end targ01;
+
+architecture behav of targ01 is
+begin
+  (o2, o1, o0) <= v;
+end behav;
diff --git a/testsuite/synth/aggr02/tb_targ01.vhdl b/testsuite/synth/aggr02/tb_targ01.vhdl
new file mode 100644
index 000000000..7f4efd64a
--- /dev/null
+++ b/testsuite/synth/aggr02/tb_targ01.vhdl
@@ -0,0 +1,28 @@
+entity tb_targ01 is
+end tb_targ01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_targ01 is
+  signal v : std_logic_vector(2 downto 0);
+  signal o0 : std_logic;
+  signal o1 : std_logic;
+  signal o2 : std_logic;
+begin
+  dut: entity work.targ01
+    port map (v, o0, o1, o2);
+
+  process
+  begin
+    v <= "010";
+    wait for 1 ns;
+    assert o2 = '0' and o1 = '1' and o0 = '0' severity failure;
+
+    v <= "101";
+    wait for 1 ns;
+    assert o2 = '1' and o1 = '0' and o0 = '1' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/aggr02/testsuite.sh b/testsuite/synth/aggr02/testsuite.sh
new file mode 100755
index 000000000..3b545a932
--- /dev/null
+++ b/testsuite/synth/aggr02/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in targ01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"