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authorTristan Gingold <tgingold@free.fr>2020-04-07 08:03:26 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-07 08:03:26 +0200
commitf9cf10cae25d288588d93bdae2ef461f040d03bc (patch)
treedafa148e0853a45326a6696fa212c08050947dd5 /testsuite/synth/aggr02/targ02.vhdl
parent63ce15f4aa9323b92348e53a285037a9c9f742bf (diff)
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testsuite/synth: add a test for target aggregate.
Diffstat (limited to 'testsuite/synth/aggr02/targ02.vhdl')
-rw-r--r--testsuite/synth/aggr02/targ02.vhdl11
1 files changed, 11 insertions, 0 deletions
diff --git a/testsuite/synth/aggr02/targ02.vhdl b/testsuite/synth/aggr02/targ02.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity targ02 is
+ port (o0, o1, o2 : out std_logic);
+end targ02;
+
+architecture behav of targ02 is
+begin
+ (o2, o1, o0) <= std_logic_vector'("001");
+end behav;