synth: add a test for previous commit (aggr).

5 files changed, 101 insertions, 0 deletions

diff --git a/testsuite/synth/aggr01/aggr01.vhdl b/testsuite/synth/aggr01/aggr01.vhdl
new file mode 100644
index 000000000..30c64c791
--- /dev/null
+++ b/testsuite/synth/aggr01/aggr01.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity aggr01 is
+  port (a : std_logic_vector (7 downto 0);
+        b : out std_logic_vector (7 downto 0));
+end aggr01;
+
+architecture behav of aggr01 is
+  constant mask : std_logic_vector (7 downto 0) :=
+    (0 => '1', others => '0');
+begin
+  b <= a and mask;
+end behav;
+    
diff --git a/testsuite/synth/aggr01/aggr02.vhdl b/testsuite/synth/aggr01/aggr02.vhdl
new file mode 100644
index 000000000..82e83ff9c
--- /dev/null
+++ b/testsuite/synth/aggr01/aggr02.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity aggr02 is
+  port (a : std_logic_vector (7 downto 0);
+        b : out std_logic_vector (7 downto 0));
+end aggr02;
+
+architecture behav of aggr02 is
+  function gen_mask (len : natural) return std_logic_vector is
+    variable res : std_logic_vector (len - 1 downto 0);
+  begin
+    res := (0 => '0', others => '1');
+    return res;
+  end gen_mask;
+
+begin
+  b <= a and gen_mask (8);
+end behav;
+    
diff --git a/testsuite/synth/aggr01/tb_aggr01.vhdl b/testsuite/synth/aggr01/tb_aggr01.vhdl
new file mode 100644
index 000000000..429117cc9
--- /dev/null
+++ b/testsuite/synth/aggr01/tb_aggr01.vhdl
@@ -0,0 +1,25 @@
+entity tb_aggr01 is
+end tb_aggr01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_aggr01 is
+  signal a, b : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.aggr01
+    port map (a, b);
+
+  process
+  begin
+    a <= x"ff";
+    wait for 1 ns;
+    assert b = x"01" severity failure;
+
+    a <= x"ee";
+    wait for 1 ns;
+    assert b = x"00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/aggr01/tb_aggr02.vhdl b/testsuite/synth/aggr01/tb_aggr02.vhdl
new file mode 100644
index 000000000..39570d788
--- /dev/null
+++ b/testsuite/synth/aggr01/tb_aggr02.vhdl
@@ -0,0 +1,25 @@
+entity tb_aggr02 is
+end tb_aggr02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_aggr02 is
+  signal a, b : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.aggr02
+    port map (a, b);
+
+  process
+  begin
+    a <= x"ff";
+    wait for 1 ns;
+    assert b = x"fe" severity failure;
+
+    a <= x"ee";
+    wait for 1 ns;
+    assert b = x"ee" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/aggr01/testsuite.sh b/testsuite/synth/aggr01/testsuite.sh
new file mode 100755
index 000000000..6086ad422
--- /dev/null
+++ b/testsuite/synth/aggr01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in aggr01 aggr02; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"