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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2022-12-19 22:11:44 +0100 |
|---|---|---|
| committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2022-12-23 23:44:14 +0100 |
| commit | 633373d0054f551158cdf668c464646bb9e6af27 (patch) | |
| tree | bc989fb2ce39865cb529ea1aa2fd957ec2d0310f /testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl | |
| parent | 5853a37df7c9468a01d62f7b2eeee7d9773e72ca (diff) | |
| download | ghdl-633373d0054f551158cdf668c464646bb9e6af27.tar.gz ghdl-633373d0054f551158cdf668c464646bb9e6af27.tar.bz2 ghdl-633373d0054f551158cdf668c464646bb9e6af27.zip | |
Added StopWatch example for DOM and documentation testing.
Diffstat (limited to 'testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl')
| -rw-r--r-- | testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl new file mode 100644 index 000000000..8daf39614 --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl @@ -0,0 +1,99 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- A generic counter module used in the StopWatch example. +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +package Utilities is + type freq is range integer'low to integer'high units + Hz; + kHz = 1000 Hz; + MHz = 1000 kHz; + GHz = 1000 MHz; + THz = 1000 GHz; + end units; + + -- deferred constant + constant IS_SIMULATION : boolean; + + function ite(condition : boolean; ThenValue : integer; ElseValue : integer) return integer; + + function log2(Value : positive) return positive; + + function bin2onehot(binary : std_logic_vector; bits : natural := 0) return std_logic_vector; + function bin2onehot(binary : unsigned; bits : natural := 0) return std_logic_vector; + + function to_index(value : unsigned; max : positive) return natural; + function to_index(value : natural; max : positive) return natural; +end package; + + +package body Utilities is + function simulation return boolean is + variable result : boolean := FALSE; + begin + -- synthesis translate_off + result := TRUE; + -- synthesis translate_on + return result; + end function; + + -- deferred constant initialization + constant IS_SIMULATION : boolean := simulation; + + function ite(condition : boolean; ThenValue : integer; ElseValue : integer) return integer is + begin + if condition then + return ThenValue; + else + return ElseValue; + end if; + end function; + + function log2(Value : positive) return positive is + variable twosPower : natural := 1; + variable result : natural := 0; + begin + while (twosPower < Value) loop + twosPower := twosPower * 2; + result := result + 1; + end loop; + return result; + end function; + + function bin2onehot(binary : std_logic_vector; bits : natural := 0) return std_logic_vector is + begin + return bin2onehot(unsigned(binary), bits); + end function; + + function bin2onehot(binary : unsigned; bits : natural := 0) return std_logic_vector is + variable result : std_logic_vector(2**binary'length - 1 downto 0) := (others => '0'); + begin + result(to_integer(binary)) := '1'; + + if (bits = 0) then + return result; + else + return result(bits - 1 downto 0); + end if; + end function; + + function to_index(value : unsigned; max : positive) return natural is + begin + return to_index(to_integer(value), max); + end function; + + function to_index(value : natural; max : positive) return natural is + begin + if (value <= max) then + return value; + else + return max; + end if; + -- return minimum(value, max); + end function; +end package body; |
