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| author | Tristan Gingold <tgingold@free.fr> | 2022-11-20 20:02:08 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-11-20 20:02:08 +0100 |
| commit | 1ea6e91b7ef11e8d7fa4679bd9cb13e91db53684 (patch) | |
| tree | 1dd3932d728dbcae31636d4ece25b36fe7637765 /testsuite/pyunit/DesignComment.vhdl | |
| parent | f722f900f4211bbddc0f432ce652e68313807ee0 (diff) | |
| download | ghdl-1ea6e91b7ef11e8d7fa4679bd9cb13e91db53684.tar.gz ghdl-1ea6e91b7ef11e8d7fa4679bd9cb13e91db53684.tar.bz2 ghdl-1ea6e91b7ef11e8d7fa4679bd9cb13e91db53684.zip | |
testsuite/pyunit: add Comments.py test
Diffstat (limited to 'testsuite/pyunit/DesignComment.vhdl')
| -rw-r--r-- | testsuite/pyunit/DesignComment.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/pyunit/DesignComment.vhdl b/testsuite/pyunit/DesignComment.vhdl new file mode 100644 index 000000000..5cd555d33 --- /dev/null +++ b/testsuite/pyunit/DesignComment.vhdl @@ -0,0 +1,14 @@ +-- No copyright for :accum: design. + +library ieee; +use ieee.std_logic_1164.all; + +entity accum is + port ( + -- :a: and :b: are the inputs of the adder. + a, b : in std_logic_vector (31 downto 0); + -- :res: is the result of the adder. + res : out std_logic_vector (31 downto 0) + ); +end accum; + |