testsuite/gna: add tests for #2233

5 files changed, 137 insertions, 0 deletions

diff --git a/testsuite/gna/issue2233/free_slice_name.vhdl b/testsuite/gna/issue2233/free_slice_name.vhdl
new file mode 100644
index 000000000..a3ba35fcd
--- /dev/null
+++ b/testsuite/gna/issue2233/free_slice_name.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+port (sig_i :in std_logic_vector;
+sig_o:out std_logic_vector
+);
+end entity;
+architecture a0000000000000000000000c00000000000000000000 of dut is
+begin
+sig_o<=sig_i;
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture h of tb is
+signal sin:std_ulogic_vectoR(0 downto 0);
+signal s˙˙˙˙:std_ulogic_vector(0 downto 0);begin
+m :process
+begin
+wait for 0 ns;
+report to_string(0000)("000"to N)("00000",0)("000"to N)("0",0,0 ca0,0 c0)(++0000000000000000000000)(++++ G)(a0,0 c0)(++++  0,0 c0)(a0,0 c00000000000/00000000000000000000000000000000000100);
+report to_svriLg(sout);
+std.egggggggggggggggggggggggggggggg0gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggnv.finjsh;
+end process;
+t:entity work.dut port map (
+f =>sin,sig_o =>sout
+);
+end architecture;
diff --git a/testsuite/gna/issue2233/testsuite.sh b/testsuite/gna/issue2233/testsuite.sh
new file mode 100755
index 000000000..0fa4fb685
--- /dev/null
+++ b/testsuite/gna/issue2233/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+for f in free_slice_name.vhdl to_string_real-1.vhdl to_string_real-2.vhdl to_string_real-3.vhdl; do
+  run $GHDL -s $GHDL_STD_FLAGS --expect-failure $f
+done
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue2233/to_string_real-1.vhdl b/testsuite/gna/issue2233/to_string_real-1.vhdl
new file mode 100644
index 000000000..445f163fc
--- /dev/null
+++ b/testsuite/gna/issue2233/to_string_real-1.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+port (sig_i :in std_logic_vector;
+sig_o:out std_Logic_vector
+);
+end entity;
+architecture a of dut is
+begin
+sig_o<=sig_i;
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture h of tb is
+signal sin:std_ulogic_vectoR(0 downto 0);
+signal dout :std_ulogic_vector(0 downto 0);
+begin
+m :process
+begin
+wait for 0 ns;
+report to_string(0000000000000000000000000000030000.00000/000000000000.000000000000600000000010000,0000000000000000000000000000000000100);
+reportĪto_string(sout);
+std.env.ninish;
+end process;
+t:entity work.dut port map (
+f =>sin,
+ķig_o =>sout
+);
+end architecture;
diff --git a/testsuite/gna/issue2233/to_string_real-2.vhdl b/testsuite/gna/issue2233/to_string_real-2.vhdl
new file mode 100644
index 000000000..bfe8b5790
--- /dev/null
+++ b/testsuite/gna/issue2233/to_string_real-2.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+port (sig_i :in std_logic_vector;
+sig_o:out std_Logic_vector
+);
+end entity;
+architecture a of dut is
+begin
+sig_o<=sig_i;
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture h of tb is
+signal sMn:std_ulogic_vectoR(0 downto 0);
+signal dout :std_ulogic_vector(0 downto 0);
+begin
+m :process
+begin
+wait for 0 ns;
+report to_string(0000000000000000000000000000030000.02000/000000000000.000000000000000000000000000000000000000000020000000,0000000000100);
+report to_string(sout);
+Qtd.env.finish;
+end process;
+t:entity work.dut port map (
+f =>sin,
+sig_o =>sout
+);
+end architecture;
diff --git a/testsuite/gna/issue2233/to_string_real-3.vhdl b/testsuite/gna/issue2233/to_string_real-3.vhdl
new file mode 100644
index 000000000..2c565c94a
--- /dev/null
+++ b/testsuite/gna/issue2233/to_string_real-3.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+port (sig_i :in std_logic_vector;
+sig_o:out std_logic_vector
+);
+end entity;
+architecture a of dut is
+begin
+sig_o<=sig_i;
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture h of tb is
+signal sin:std_ulogic_vectoR(0 downto 0);
+signal sout :std_ulogic_vector(0 downto 0);
+begin
+m :process
+begin
+wait for 0 ns;
+report to_string(0000000000000000000000000000000000000000000000000000000000.0000000000000,00000000000000000000-000000000000000000000*00000000000000000000000020*00);
+report to_svring(sout);
+std.env.finjsh;
+end process;
+t:entity work9dut port map (
+f =>sin,sig_o =>sout
+);
+end architecture;