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| author | Tristan Gingold <tgingold@free.fr> | 2014-12-07 11:40:58 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2014-12-07 11:40:58 +0100 |
| commit | 2f4337f027ec97dd93642ea2db70873e9192fb3b (patch) | |
| tree | d8c63b4cef84e33bae4e7018ce7abc07e0e3bd3c /testsuite/gna/perf02/ilb_table.vhd | |
| parent | abe17103c669922a7349a7b2238d440b24d29f30 (diff) | |
| download | ghdl-2f4337f027ec97dd93642ea2db70873e9192fb3b.tar.gz ghdl-2f4337f027ec97dd93642ea2db70873e9192fb3b.tar.bz2 ghdl-2f4337f027ec97dd93642ea2db70873e9192fb3b.zip | |
Add perf02 (performance issue).
Diffstat (limited to 'testsuite/gna/perf02/ilb_table.vhd')
| -rw-r--r-- | testsuite/gna/perf02/ilb_table.vhd | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/testsuite/gna/perf02/ilb_table.vhd b/testsuite/gna/perf02/ilb_table.vhd new file mode 100644 index 000000000..ea4455b90 --- /dev/null +++ b/testsuite/gna/perf02/ilb_table.vhd @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity ilb_table is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(31 downto 0); + ra0_addr : in std_logic_vector(4 downto 0) + ); +end ilb_table; +architecture augh of ilb_table is + + -- Embedded RAM + + type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); + signal ram : ram_type := ("00000000000000000000100000000000", "00000000000000000000100000101101", "00000000000000000000100001011011", "00000000000000000000100010001010", "00000000000000000000100010111001", "00000000000000000000100011101010", "00000000000000000000100100011100", "00000000000000000000100101001111", "00000000000000000000100110000011", "00000000000000000000100110111001", "00000000000000000000100111101111", "00000000000000000000101000100111", "00000000000000000000101001100000", "00000000000000000000101010011010", "00000000000000000000101011010110", "00000000000000000000101100010010", "00000000000000000000101101010000", "00000000000000000000101110010000", "00000000000000000000101111010001", "00000000000000000000110000010011", "00000000000000000000110001010110", "00000000000000000000110010011100", "00000000000000000000110011100010", "00000000000000000000110100101011", "00000000000000000000110101110100", "00000000000000000000110111000000", "00000000000000000000111000001101", "00000000000000000000111001011100", "00000000000000000000111010101100", "00000000000000000000111011111110", "00000000000000000000111101010010", "00000000000000000000111110101000"); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- The component is a ROM. + -- There is no Write side. + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; |