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| author | Tristan Gingold <tgingold@free.fr> | 2020-08-07 06:54:26 +0200 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2020-08-07 06:54:26 +0200 |
| commit | 606bd7942d0b2d4c7e4a9cbb51afb8818215ccaf (patch) | |
| tree | 427fdd1116673ae243a59093f076b432151ea1eb /testsuite/gna/issue887/test.vhdl | |
| parent | f7d66d624f850d2b015bacc2dc82e5605bfb5fdf (diff) | |
| download | ghdl-606bd7942d0b2d4c7e4a9cbb51afb8818215ccaf.tar.gz ghdl-606bd7942d0b2d4c7e4a9cbb51afb8818215ccaf.tar.bz2 ghdl-606bd7942d0b2d4c7e4a9cbb51afb8818215ccaf.zip | |
testsuite/gna: add a test for #887
Diffstat (limited to 'testsuite/gna/issue887/test.vhdl')
| -rw-r--r-- | testsuite/gna/issue887/test.vhdl | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/testsuite/gna/issue887/test.vhdl b/testsuite/gna/issue887/test.vhdl new file mode 100644 index 000000000..1178b597c --- /dev/null +++ b/testsuite/gna/issue887/test.vhdl @@ -0,0 +1,58 @@ +library ieee; +use ieee.fixed_float_types.all; +use ieee.fixed_pkg.all; + +package filtPkg is + type u_sfixed_array is array (integer range <>) of u_sfixed; +end package filtPkg; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.fixed_float_types.all; +use ieee.fixed_pkg.all; +use work.filtpkg.all; + +entity filter is + generic ( + intbits_g: natural; + decbits_g: natural + ); + port ( + clk: in std_ulogic; + c: in u_sfixed_array + ); +end entity filter; + +architecture rtl of filter +is + signal tmp: u_sfixed (intbits_g - 1 downto - decbits_g); +begin + tmp <= c (0); +end architecture rtl; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.fixed_float_types.all; +use ieee.fixed_pkg.all; +use work.filtpkg.all; + +entity tb is +end entity tb; + +architecture test of tb +is + constant intbits_c: natural := 4; + constant decbits_c: natural := 6; + signal clk: std_ulogic := '0'; + signal done: boolean := false; + signal coeff: u_sfixed_array (0 to 5) (intbits_c - 1 downto - decbits_c) := (others => (others => '0')); + signal tmp: u_sfixed (intbits_c - 1 downto - decbits_c); +begin + clk <= transport not clk after 10 ns when not done else '0'; + done <= transport true after 500 ns; + tmp <= coeff (0); + filter_1: entity work.filter + generic map (intbits_g => intbits_c, decbits_g => decbits_c) + port map (clk => clk, c => coeff); +end architecture test; + |