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author | Tristan Gingold <tgingold@free.fr> | 2019-05-11 07:44:18 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-11 18:13:38 +0200 |
commit | b3e340b0fbef7e7043f9626ee6d37a69f10edfe8 (patch) | |
tree | 344b0d75d3ef8fb782e6fe186ea378ad73ccaf49 /testsuite/gna/issue818/tc1.vhdl | |
parent | 36b54159513f10891fb206789f8d2d2c6f8e91fd (diff) | |
download | ghdl-b3e340b0fbef7e7043f9626ee6d37a69f10edfe8.tar.gz ghdl-b3e340b0fbef7e7043f9626ee6d37a69f10edfe8.tar.bz2 ghdl-b3e340b0fbef7e7043f9626ee6d37a69f10edfe8.zip |
Add testcases for #818
Diffstat (limited to 'testsuite/gna/issue818/tc1.vhdl')
-rw-r--r-- | testsuite/gna/issue818/tc1.vhdl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/gna/issue818/tc1.vhdl b/testsuite/gna/issue818/tc1.vhdl new file mode 100644 index 000000000..ff2cc0775 --- /dev/null +++ b/testsuite/gna/issue818/tc1.vhdl @@ -0,0 +1,17 @@ +entity tc1 is +end; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tc1 is + signal clk : std_logic; + signal tg : std_logic; +begin + process (clk) is + begin + if ?? tg then + null; + end if; + end process; +end behav; |