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author | Tristan Gingold <tgingold@free.fr> | 2018-12-26 06:07:42 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-12-26 06:59:48 +0100 |
commit | 752306411171634308ba1469332ae008b51116fa (patch) | |
tree | ddb167496a642d168158ce88dffa2e990dac1088 /testsuite/gna/issue719/tb.vhdl | |
parent | b19787b12897fed179053e87cc6a468ca306d799 (diff) | |
download | ghdl-752306411171634308ba1469332ae008b51116fa.tar.gz ghdl-752306411171634308ba1469332ae008b51116fa.tar.bz2 ghdl-752306411171634308ba1469332ae008b51116fa.zip |
Add testcase for #719
Diffstat (limited to 'testsuite/gna/issue719/tb.vhdl')
-rw-r--r-- | testsuite/gna/issue719/tb.vhdl | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/gna/issue719/tb.vhdl b/testsuite/gna/issue719/tb.vhdl new file mode 100644 index 000000000..e911ae090 --- /dev/null +++ b/testsuite/gna/issue719/tb.vhdl @@ -0,0 +1,31 @@ + library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +entity test_tb is +port( + dout : std_logic +); +end entity; + +architecture sim of test_tb is + + signal rst : std_logic := '1'; + signal clk : std_logic := '1'; + signal din : std_logic ; + + type myrec is + record + rst : std_logic; + vld : std_logic; + end record; + + procedure myproc( + variable din : in std_logic; + variable dout : out std_logic + ) is + begin + dout := din; + end procedure; + +begin +end architecture; |