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author | Tristan Gingold <tgingold@free.fr> | 2018-10-24 20:41:01 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-10-24 20:41:01 +0200 |
commit | 505a68018797612c4d88f1f871a2450a93a15767 (patch) | |
tree | a0c548c9f2489ebbc5d0139f5ae68b18918d1cbd /testsuite/gna/issue663/repro.vhdl | |
parent | 47a0b02c8c9175389d0ac0a44ef1b9a9a6521503 (diff) | |
download | ghdl-505a68018797612c4d88f1f871a2450a93a15767.tar.gz ghdl-505a68018797612c4d88f1f871a2450a93a15767.tar.bz2 ghdl-505a68018797612c4d88f1f871a2450a93a15767.zip |
Add testcase for #663
Diffstat (limited to 'testsuite/gna/issue663/repro.vhdl')
-rw-r--r-- | testsuite/gna/issue663/repro.vhdl | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/gna/issue663/repro.vhdl b/testsuite/gna/issue663/repro.vhdl new file mode 100644 index 000000000..220c4820f --- /dev/null +++ b/testsuite/gna/issue663/repro.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro is +end entity repro; + +architecture a of repro is + signal clk : std_logic := '0'; + + signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000"; + alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5); + + procedure check_stable( + signal clock : in std_logic; + signal expr : in std_logic_vector) is + begin + wait until rising_edge(clock); + end; + +begin + clock : process is + begin + clk <= '1', '0' after 5 ns; + wait; + end process clock; + +-- process +-- begin +-- check_stable(clk, check_stable_expr_1); +-- wait on clk, check_stable_expr_1; +-- assert check_stable_expr_1 = "000"; +-- end process; + check_stable_1 : check_stable(clk, check_stable_expr_1); + +end architecture; |