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authorTristan Gingold <tgingold@free.fr>2020-06-25 07:48:01 +0200
committerTristan Gingold <tgingold@free.fr>2020-06-25 07:48:01 +0200
commitd85a1a9dcc4ebe3bafc746ea27ba38c5c7f78681 (patch)
tree53a5f6512a3b39f998bdc9aea3ca06f9332522a1 /testsuite/gna/issue641/repro1.vhdl
parentda3ee484fba29fcb976cfe6973a3a7b0dcb25f80 (diff)
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testsuite/gna: add tests for #641
Diffstat (limited to 'testsuite/gna/issue641/repro1.vhdl')
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diff --git a/testsuite/gna/issue641/repro1.vhdl b/testsuite/gna/issue641/repro1.vhdl
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+entity repro1b is
+ port (b : bit_vector);
+end entity;
+
+architecture a of repro1b is
+ signal c : b'subtype;
+begin
+ c <= b;
+ assert c'left = 7;
+ assert c'right = 0;
+end architecture;
+
+entity repro1 is
+end entity;
+
+architecture tb of repro1 is
+ signal s : bit_vector(7 downto 0);
+begin
+ DUT: entity work.repro1b
+ port map (b => s);
+end architecture;
+