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| author | Tristan Gingold <tgingold@free.fr> | 2018-07-22 03:26:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-07-22 03:26:48 +0200 |
| commit | bb39004f1086e3fbbf5933ac880f0bb396c27cd0 (patch) | |
| tree | 6c7f1df67f6783a03991f870fad624813c54b78f /testsuite/gna/issue626/top.vhdl | |
| parent | d3b9380ac7dcaf6bd90a7460f39db6b82568d705 (diff) | |
| download | ghdl-bb39004f1086e3fbbf5933ac880f0bb396c27cd0.tar.gz ghdl-bb39004f1086e3fbbf5933ac880f0bb396c27cd0.tar.bz2 ghdl-bb39004f1086e3fbbf5933ac880f0bb396c27cd0.zip | |
Add testcase for #626
Diffstat (limited to 'testsuite/gna/issue626/top.vhdl')
| -rw-r--r-- | testsuite/gna/issue626/top.vhdl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/gna/issue626/top.vhdl b/testsuite/gna/issue626/top.vhdl new file mode 100644 index 000000000..8deea15f6 --- /dev/null +++ b/testsuite/gna/issue626/top.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity inc_ent is + generic ( + works : integer; + vec : std_logic_vector); +end entity; + +architecture default of inc_ent is +begin + assert false report integer'image(works) & " " & integer'image(vec'length); +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +entity top_ent is end entity; + +architecture default of top_ent is + constant foo_v : std_logic_vector(0 to 12) := (others => '1'); +begin + g : for ix in 0 to 4 generate + constant foo_v : std_logic_vector(0 to ix) := (others => '1'); + begin + + inst : entity work.inc_ent + generic map ( + works => 0, + vec => (0 to ix => '1') + ); + inst2 : entity work.inc_ent + generic map ( + works => 1, + vec => foo_v + ); + end generate; +end architecture; |