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author | Tristan Gingold <tgingold@free.fr> | 2018-03-15 21:02:02 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-03-17 07:07:46 +0100 |
commit | 0edf0a10c5f2f45c92bdce6d0f80de9790e205fa (patch) | |
tree | 69c0cb2681884c15007e930ac12784fa290372e4 /testsuite/gna/issue542/write.vhd | |
parent | 1ea2bc4ab4ae43273094dc798244fc864d2d6198 (diff) | |
download | ghdl-0edf0a10c5f2f45c92bdce6d0f80de9790e205fa.tar.gz ghdl-0edf0a10c5f2f45c92bdce6d0f80de9790e205fa.tar.bz2 ghdl-0edf0a10c5f2f45c92bdce6d0f80de9790e205fa.zip |
Add testcase for #542
Diffstat (limited to 'testsuite/gna/issue542/write.vhd')
-rw-r--r-- | testsuite/gna/issue542/write.vhd | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/gna/issue542/write.vhd b/testsuite/gna/issue542/write.vhd new file mode 100644 index 000000000..d7c1fd129 --- /dev/null +++ b/testsuite/gna/issue542/write.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity write is + port( + clk : in std_logic; + reset : in std_logic; + write : in std_logic; + ack : out std_logic +); +end write; + +architecture a of write is +begin + + process (clk, reset) is + begin + if reset = '1' then + ack <= '0'; + elsif rising_edge(clk) then + if write = '1' then + ack <= '1'; + else + ack <= '0'; + end if; + end if; + end process; + +end architecture; |