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authorTristan Gingold <tgingold@free.fr>2018-03-15 21:02:02 +0100
committerTristan Gingold <tgingold@free.fr>2018-03-17 07:07:46 +0100
commit0edf0a10c5f2f45c92bdce6d0f80de9790e205fa (patch)
tree69c0cb2681884c15007e930ac12784fa290372e4 /testsuite/gna/issue542/write.vhd
parent1ea2bc4ab4ae43273094dc798244fc864d2d6198 (diff)
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Add testcase for #542
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diff --git a/testsuite/gna/issue542/write.vhd b/testsuite/gna/issue542/write.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity write is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ write : in std_logic;
+ ack : out std_logic
+);
+end write;
+
+architecture a of write is
+begin
+
+ process (clk, reset) is
+ begin
+ if reset = '1' then
+ ack <= '0';
+ elsif rising_edge(clk) then
+ if write = '1' then
+ ack <= '1';
+ else
+ ack <= '0';
+ end if;
+ end if;
+ end process;
+
+end architecture;