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author | Tristan Gingold <tgingold@free.fr> | 2018-02-03 14:53:53 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-02-03 14:53:53 +0100 |
commit | e871dd0790360e4a88bd8337047aa93593be64e4 (patch) | |
tree | edae4771f35cb9de685339144e69665ce16dd923 /testsuite/gna/issue524/cond.vhdl | |
parent | 2f647d9fd9d6f15dfaf2d9a8971f8e3f36563b60 (diff) | |
download | ghdl-e871dd0790360e4a88bd8337047aa93593be64e4.tar.gz ghdl-e871dd0790360e4a88bd8337047aa93593be64e4.tar.bz2 ghdl-e871dd0790360e4a88bd8337047aa93593be64e4.zip |
Add testcase for #524
Diffstat (limited to 'testsuite/gna/issue524/cond.vhdl')
-rw-r--r-- | testsuite/gna/issue524/cond.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/gna/issue524/cond.vhdl b/testsuite/gna/issue524/cond.vhdl new file mode 100644 index 000000000..5954b1e6c --- /dev/null +++ b/testsuite/gna/issue524/cond.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cond is + port (i, rst, clk : std_logic; + o : out std_logic); +end; + +architecture behav of cond is +begin + process (clk) is + begin + if rising_edge(clk) then + if rst then + o <= '0'; + else + o <= i; + end if; + end if; + end process; +end; |