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author | Tristan Gingold <tgingold@free.fr> | 2016-04-02 07:40:37 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-04-02 07:40:37 +0200 |
commit | 66e31d6d8c4faab0aeadee87298f13a3b67adbfb (patch) | |
tree | af863500c6e1ddf22321538a6c51247fccd57704 /testsuite/gna/issue50/vector.d/cmp_132.vhd | |
parent | 122fa90fb7e5c15b58efa100da828c1e879b4e4e (diff) | |
download | ghdl-66e31d6d8c4faab0aeadee87298f13a3b67adbfb.tar.gz ghdl-66e31d6d8c4faab0aeadee87298f13a3b67adbfb.tar.bz2 ghdl-66e31d6d8c4faab0aeadee87298f13a3b67adbfb.zip |
Add testcase for issue50.
Diffstat (limited to 'testsuite/gna/issue50/vector.d/cmp_132.vhd')
-rw-r--r-- | testsuite/gna/issue50/vector.d/cmp_132.vhd | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/gna/issue50/vector.d/cmp_132.vhd b/testsuite/gna/issue50/vector.d/cmp_132.vhd new file mode 100644 index 000000000..12cbe3918 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_132.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_132 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_132; + +architecture augh of cmp_132 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; |