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| author | Tristan Gingold <tgingold@free.fr> | 2016-12-22 06:55:04 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-12-22 06:55:04 +0100 |
| commit | fc713626e51847a501c22c5b7d6dfda88e1d0183 (patch) | |
| tree | 8cde82b44cf3fad05788edaaf90babe578c997ee /testsuite/gna/issue43 | |
| parent | 6a25af7e804b49c5c3a8b64cd020f483b9607bce (diff) | |
| download | ghdl-fc713626e51847a501c22c5b7d6dfda88e1d0183.tar.gz ghdl-fc713626e51847a501c22c5b7d6dfda88e1d0183.tar.bz2 ghdl-fc713626e51847a501c22c5b7d6dfda88e1d0183.zip | |
issue43: add a file.
Diffstat (limited to 'testsuite/gna/issue43')
| -rw-r--r-- | testsuite/gna/issue43/repro3.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/gna/issue43/repro3.vhdl b/testsuite/gna/issue43/repro3.vhdl new file mode 100644 index 000000000..ea43dd53e --- /dev/null +++ b/testsuite/gna/issue43/repro3.vhdl @@ -0,0 +1,24 @@ +entity test_tb is
+end entity;
+
+architecture beh of test_tb is
+ signal rx_data : bit_vector(159 downto 0);
+
+ procedure to_t( signal sa : out bit_vector(31 downto 0)) is
+ begin
+ sa <= (others => '1');
+ assert false report "lol";
+ end procedure;
+begin
+ asd : for i in 0 to 4 generate
+ begin
+ process
+ subtype rng1 is natural range 32*(i+1)-1 downto 32*i;
+ begin
+ wait for 10 ns;
+ to_t(rx_data(rng1));
+ wait;
+ end process;
+ end generate;
+
+end architecture;
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