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author | Tristan Gingold <tgingold@free.fr> | 2018-03-24 17:44:40 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-03-24 17:44:40 +0100 |
commit | 156005b67550ead369c6ab1149e2791a42c7c895 (patch) | |
tree | 5dac084dbc39c5913540fa53a154f1262d060ef5 /testsuite/gna/issue381/test.vhdl | |
parent | 1fd1663e94f9d1c14fb8ccf8f1ee034827f7c31a (diff) | |
download | ghdl-156005b67550ead369c6ab1149e2791a42c7c895.tar.gz ghdl-156005b67550ead369c6ab1149e2791a42c7c895.tar.bz2 ghdl-156005b67550ead369c6ab1149e2791a42c7c895.zip |
Add reproducer for #381.
Diffstat (limited to 'testsuite/gna/issue381/test.vhdl')
-rw-r--r-- | testsuite/gna/issue381/test.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/gna/issue381/test.vhdl b/testsuite/gna/issue381/test.vhdl new file mode 100644 index 000000000..5c988a7da --- /dev/null +++ b/testsuite/gna/issue381/test.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity can_rx is + port ( + demo : in std_logic; + status : out std_logic_vector (31 downto 0) + ); +end can_rx; + +architecture rtl of can_rx is +begin + status(0) <= (0=>'0', others => '0') when demo = '1' else (0=>'1', others => '0'); +end rtl; |