Add testcase for #317

3 files changed, 439 insertions, 0 deletions

diff --git a/testsuite/gna/issue317/PoC/tb/common/config_tb.vhdl b/testsuite/gna/issue317/PoC/tb/common/config_tb.vhdl
new file mode 100644
index 000000000..1b9ab0f82
--- /dev/null
+++ b/testsuite/gna/issue317/PoC/tb/common/config_tb.vhdl
@@ -0,0 +1,81 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors:					Thomas B. Preusser
+--									Patrick Lehmann
+--
+-- Testbench:				Tests global constants, functions and settings
+--
+-- Description:
+-- ------------------------------------
+--		TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+--										 Chair of VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--		http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library	PoC;
+use			PoC.config.all;
+use			PoC.utils.all;
+-- simulation only packages
+use			PoC.sim_types.all;
+use			PoC.simulation.all;
+
+
+entity config_tb is
+end config_tb;
+
+
+architecture tb of config_tb is
+	signal SimQuiet		: boolean		:= true;
+begin
+
+	procChecker : process
+		constant simProcessID	: T_SIM_PROCESS_ID := simRegisterProcess("Checker");
+	begin
+		if not SimQuiet then
+			report "is simulation?:    " & boolean'image(SIMULATION)							severity note;
+			report "Vendor:            " & T_VENDOR'image(VENDOR)									severity note;
+			report "Device:            " & T_DEVICE'image(DEVICE)									severity note;
+			report "Device Family:     " & T_DEVICE_FAMILY'image(DEVICE_FAMILY)		severity note;
+			report "Device Subtype:    " & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE)	severity note;
+			report "Device Series:     " & T_DEVICE_SERIES'image(DEVICE_SERIES)		severity note;
+			report "Device Generation: " & integer'image(DEVICE_GENERATION)				severity note;
+			report "Device Number:     " & integer'image(DEVICE_NUMBER)						severity note;
+			report "--------------------------------------------------"						severity note;
+			report "LUT fan-in:        " & integer'image(LUT_FANIN)								severity note;
+			report "Transceiver:       " & T_TRANSCEIVER'image(TRANSCEIVER_TYPE)	severity note;
+		end if;
+
+		simAssertion((SIMULATION = TRUE),												"SIMULATION="					& boolean'image(SIMULATION)											&	"    Expected=TRUE");
+		simAssertion((VENDOR = VENDOR_GENERIC),									"VENDOR= "						& T_VENDOR'image(VENDOR)												&	"    Expected=VENDOR_XILINX");
+		simAssertion((DEVICE = DEVICE_GENERIC),									"DEVICE="							& T_DEVICE'image(DEVICE)												&	"    Expected=DEVICE_KINTEX7");
+		simAssertion((DEVICE_FAMILY = DEVICE_FAMILY_GENERIC),		"DEVICE_FAMILY="			& T_DEVICE_FAMILY'image(DEVICE_FAMILY)					&	"    Expected=DEVICE_FAMILY_KINTEX");
+		simAssertion((DEVICE_NUMBER = 0),												"DEVICE_NUMBER="			& integer'image(DEVICE_NUMBER)									&	"    Expected=325");
+		simAssertion((DEVICE_SUBTYPE = DEVICE_SUBTYPE_GENERIC),	"DEVICE_SUBTYPE="			& T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE)				&	"    Expected=DEVICE_SUBTYPE_T");
+		simAssertion((DEVICE_GENERATION = 0),										"DEVICE_GENERATION="	& integer'image(DEVICE_GENERATION)							&	"    Expected=7");
+		simAssertion((DEVICE_SERIES = DEVICE_SERIES_GENERIC),		"DEVICE_SERIES="			& T_DEVICE_SERIES'image(DEVICE_SERIES)					&	"    Expected=DEVICE_SERIES_7_SERIES");
+		simAssertion((LUT_FANIN = 6),														"LUT_FANIN="					& integer'image(LUT_FANIN)											&	"    Expected=6");
+		simAssertion((TRANSCEIVER_TYPE = TRANSCEIVER_GENERIC),	"TRANSCEIVER_TYPE="		& T_TRANSCEIVER'image(TRANSCEIVER_TYPE)					&	"    Expected=TRANSCEIVER_GTXE2");
+
+		-- This process is finished
+		simDeactivateProcess(simProcessID);
+		wait;  -- forever
+	end process;
+end architecture;
diff --git a/testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl b/testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl
new file mode 100644
index 000000000..b7f015674
--- /dev/null
+++ b/testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl
@@ -0,0 +1,233 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors:					Patrick Lehmann
+--
+-- Module:					TODO
+--
+-- Description:
+-- ------------------------------------
+--		TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+--										 Chair of VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--		http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use			IEEE.STD_LOGIC_1164.all;
+use			IEEE.NUMERIC_STD.all;
+
+library OSVVM;
+use			OSVVM.RandomPkg.all;
+
+library PoC;
+use			PoC.math.all;
+use			PoC.utils.all;
+use			PoC.vectors.all;
+use			PoC.strings.all;
+use			PoC.physical.all;
+-- simulation only packages
+use			PoC.sim_types.all;
+use			PoC.simulation.all;
+use			PoC.waveform.all;
+
+library Test;
+
+
+entity sortnet_BitonicSort_tb is
+end entity;
+
+
+architecture tb of sortnet_BitonicSort_tb is
+	constant TAG_BITS								: positive	:= 4;
+
+	constant INPUTS									: positive	:= 64;
+	constant DATA_COLUMNS						: positive	:= 2;
+
+	constant KEY_BITS								: positive	:= 32;
+	constant DATA_BITS							: positive	:= 64;
+	constant META_BITS							: positive	:= TAG_BITS;
+	constant PIPELINE_STAGE_AFTER		: natural		:= 2;
+
+	constant LOOP_COUNT							: positive	:= 32; -- 1024;
+
+	constant STAGES									: positive	:= triangularNumber(log2ceil(INPUTS));
+	constant DELAY									: natural		:= STAGES / PIPELINE_STAGE_AFTER;
+
+	package P_SORTNET_TB is new Test.sortnet_tb
+		generic map (
+			META_BITS		=> META_BITS,
+			DATA_BITS		=> DATA_BITS,
+			INPUTS			=> INPUTS
+		);
+	use P_SORTNET_TB.all;
+
+	constant CLOCK_FREQ					: FREQ																			:= 100 MHz;
+	signal Clock								: std_logic																	:= '1';
+
+	signal Generator_Valid			: std_logic																	:= '0';
+	signal Generator_IsKey			: std_logic																	:= '0';
+	signal Generator_Data				: T_DATA_VECTOR(INPUTS - 1 downto 0)				:= (others => (others => '0'));
+	signal Generator_Meta				: std_logic_vector(META_BITS - 1 downto 0)	:= (others => '0');
+
+	signal Sort_Valid						: std_logic;
+	signal Sort_IsKey						: std_logic;
+	signal Sort_Data						: T_DATA_VECTOR(INPUTS - 1 downto 0);
+	signal Sort_Meta						: std_logic_vector(META_BITS - 1 downto 0);
+
+	signal DataInputMatrix			: T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
+	signal DataOutputMatrix			: T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
+
+	shared variable ScoreBoard	: PT_SCOREBOARD;
+
+begin
+	-- initialize global simulation status
+	simInitialize;
+
+	simWriteMessage("SETTINGS");
+	simWriteMessage("  INPUTS:    " & integer'image(INPUTS));
+	simWriteMessage("  KEY_BITS:  " & integer'image(KEY_BITS));
+	simWriteMessage("  DATA_BITS: " & integer'image(DATA_BITS));
+	simWriteMessage("  REG AFTER: " & integer'image(PIPELINE_STAGE_AFTER));
+
+	simGenerateClock(Clock, CLOCK_FREQ);
+
+	procGenerator : process
+		constant simProcessID			: T_SIM_PROCESS_ID		:= simRegisterProcess("Generator");
+		variable RandomVar				: RandomPType;					-- protected type from RandomPkg
+
+		variable KeyInput					: std_logic_vector(KEY_BITS - 1 downto 0);
+		variable DataInput				: std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0);
+		variable TagInput					: std_logic_vector(TAG_BITS - 1 downto 0);
+		variable Generator_Input	: T_DATA_VECTOR(INPUTS - 1 downto 0);
+
+		function GreaterThan(L : std_logic_vector; R : std_logic_vector) return boolean is
+			alias LL is L(KEY_BITS - 1 downto 0);
+			alias RR is R(KEY_BITS - 1 downto 0);
+		begin
+			return unsigned(LL) > unsigned(RR);
+		end function;
+
+		variable ScoreBoardData	: T_SCOREBOARD_DATA;
+	begin
+		RandomVar.InitSeed(RandomVar'instance_name);		-- Generate initial seeds
+
+		Generator_Valid		<= '0';
+		Generator_IsKey		<= '0';
+		Generator_Input		:= (others => (others => '0'));
+		Generator_Meta		<= (others => '0');
+		wait until rising_edge(Clock);
+
+		Generator_Valid		<= '1';
+		for i in 0 to LOOP_COUNT - 1 loop
+--			report "Loop: " & integer'image (i) severity note;
+		  TagInput							:= RandomVar.RandSlv(TAG_BITS);
+
+			ScoreBoardData.IsKey	:= to_sl(i mod DATA_COLUMNS = 0);
+			ScoreBoardData.Meta		:= resize(TagInput, META_BITS);
+			Generator_IsKey				<= ScoreBoardData.IsKey;
+			Generator_Meta				<= ScoreBoardData.Meta;
+
+			KeyInput							:= RandomVar.RandSlv(KEY_BITS);
+			DataInput							:= RandomVar.RandSlv(DATA_BITS - KEY_BITS);
+			Generator_Input(0)		:= DataInput & KeyInput;
+			ScoreBoardData.Data(0):= Generator_Input(0);
+
+			loop_j: for j in 1 to INPUTS - 1 loop
+				KeyInput						:= RandomVar.RandSlv(KEY_BITS);
+				DataInput						:= RandomVar.RandSlv(DATA_BITS - KEY_BITS);
+				Generator_Input(j)	:= DataInput & KeyInput;
+
+				for k in j downto 1 loop
+					if GreaterThan(ScoreBoardData.Data(k - 1), Generator_Input(j)) then
+						ScoreBoardData.Data(k)	:= ScoreBoardData.Data(k - 1);
+					else
+						ScoreBoardData.Data(k)	:= Generator_Input(j);
+						next loop_j;
+					end if;
+				end loop;
+				ScoreBoardData.Data(0)	:= Generator_Input(j);
+			end loop;
+
+			Generator_Data				<= Generator_Input;
+			ScoreBoard.Push(ScoreBoardData);
+			wait until rising_edge(Clock);
+		end loop;
+
+		Generator_Valid				<= '0';
+		wait until rising_edge(Clock);
+
+		-- This process is finished
+		simDeactivateProcess(simProcessID);
+		wait;		-- forever
+	end process;
+
+	DataInputMatrix		<= to_slm(Generator_Data);
+
+	sort : entity PoC.sortnet_BitonicSort
+		generic map (
+			INPUTS								=> INPUTS,
+			KEY_BITS							=> KEY_BITS,
+			DATA_BITS							=> DATA_BITS,
+			META_BITS							=> META_BITS,
+			PIPELINE_STAGE_AFTER	=> PIPELINE_STAGE_AFTER
+		)
+		port map (
+			Clock				=> Clock,
+			Reset				=> '0',
+
+			In_Valid		=> Generator_Valid,
+			In_IsKey		=> Generator_IsKey,
+			In_Data			=> DataInputMatrix,
+			In_Meta			=> Generator_Meta,
+
+			Out_Valid		=> Sort_Valid,
+			Out_IsKey		=> Sort_IsKey,
+			Out_Data		=> DataOutputMatrix,
+			Out_Meta		=> Sort_Meta
+		);
+
+	Sort_Data	<= to_dv(DataOutputMatrix);
+
+	procChecker : process
+		constant simProcessID		: T_SIM_PROCESS_ID		:= simRegisterProcess("Checker");
+		variable Check					: boolean;
+		variable CurValue				: unsigned(KEY_BITS - 1 downto 0);
+		variable LastValue			: unsigned(KEY_BITS - 1 downto 0);
+
+		variable ScoreBoardData	: T_SCOREBOARD_DATA;
+	begin
+		wait until rising_edge(Sort_Valid);
+
+		for i in 0 to LOOP_COUNT - 1 loop
+			wait until falling_edge(Clock);
+
+			Check		:= TRUE;
+			ScoreBoardData.IsKey	:= Sort_IsKey;
+			ScoreBoardData.Meta		:= Sort_Meta;
+			ScoreBoardData.Data		:= Sort_Data;
+			ScoreBoard.Check(ScoreBoardData);
+		end loop;
+		-- simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue)));
+
+		-- This process is finished
+		simDeactivateProcess(simProcessID);
+		wait;  -- forever
+	end process;
+end architecture;
diff --git a/testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_tb.pkg.vhdl b/testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_tb.pkg.vhdl
new file mode 100644
index 000000000..a70137a74
--- /dev/null
+++ b/testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_tb.pkg.vhdl
@@ -0,0 +1,125 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors:					Patrick Lehmann
+--
+-- Module:					TODO
+--
+-- Description:
+-- ------------------------------------
+--		TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+--										 Chair of VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--		http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use			IEEE.STD_LOGIC_1164.all;
+use			IEEE.NUMERIC_STD.all;
+
+library OSVVM;
+
+library PoC;
+use			PoC.utils.all;
+use			PoC.vectors.all;
+use			PoC.strings.all;
+
+
+package sortnet_tb is
+	generic (
+		META_BITS			: positive;
+		DATA_BITS			: positive;
+		INPUTS				: positive
+	);
+
+	subtype T_DATA				is std_logic_vector(DATA_BITS - 1 downto 0);
+	type T_DATA_VECTOR		is array(natural range <>) of T_DATA;
+
+	function to_dv(slm : T_SLM) return T_DATA_VECTOR;
+	function to_slm(dv : T_DATA_VECTOR) return T_SLM;
+
+	type T_SCOREBOARD_DATA is record
+		IsKey : std_logic;
+		Meta  : std_logic_vector(META_BITS - 1 downto 0);
+		Data  : T_DATA_VECTOR(INPUTS - 1 downto 0);
+	end record;
+
+	function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean;
+	function to_string(dataset : T_SCOREBOARD_DATA) return string;
+
+	package P_SCOREBOARD is new OSVVM.ScoreboardGenericPkg
+		generic map (
+			ExpectedType        => T_SCOREBOARD_DATA,
+			ActualType          => T_SCOREBOARD_DATA,
+			Match               => match,
+			expected_to_string  => to_string, --[T_SCOREBOARD_DATA return string],
+			actual_to_string    => to_string
+		);
+
+	alias PT_SCOREBOARD is P_SCOREBOARD.ScoreBoardPType;
+end package;
+
+
+package body sortnet_tb is
+	function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is
+		variable good : boolean;
+	begin
+		good :=						(expected.IsKey = actual.IsKey);
+		good := good and	(expected.Meta = actual.Meta);
+		if (expected.IsKey = '1') then
+			for i in expected.Data'range loop
+				good := good and	(expected.Data(i) = actual.Data(i));
+				exit when (good = FALSE);
+			end loop;
+		end if;
+		return good;
+	end function;
+
+	function to_string(dataset : T_SCOREBOARD_DATA) return string is
+		variable KeyMarker : string(1 to 2);
+	begin
+		KeyMarker := ite((dataset.IsKey = '1'), "* ", "  ");
+		-- for i in 0 to 0 loop --dataset.Key'range loop
+			return	"Data: " & to_string(dataset.Data(0), 'h') & KeyMarker &
+						"  Meta: " & to_string(dataset.Meta, 'h');
+		-- end loop;
+	end function;
+
+	function to_dv(slm : T_SLM) return T_DATA_VECTOR is
+		variable Result	: T_DATA_VECTOR(slm'range(1));
+	begin
+		for i in slm'high(1) downto slm'low(1) loop
+			for j in T_DATA'range loop
+				Result(i)(j)	:= slm(i, j);
+			end loop;
+		end loop;
+		return Result;
+	end function;
+
+	function to_slm(dv : T_DATA_VECTOR) return T_SLM is
+		variable Result	: T_SLM(dv'range, T_DATA'range);
+	begin
+		for i in dv'range loop
+			for j in T_DATA'range loop
+				Result(i, j)	:= dv(i)(j);
+			end loop;
+		end loop;
+		return Result;
+	end function;
+end package body;