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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-02 07:40:14 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-02 07:40:14 +0200 |
| commit | 87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869 (patch) | |
| tree | 237dcf1674057fbeb1e1bf7125a72aa5b5669d40 /testsuite/gna/issue2116/attr5.vhdl | |
| parent | 9b5de7a92a6ae8980bcaad0d1c87f0938c337f21 (diff) | |
| download | ghdl-87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869.tar.gz ghdl-87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869.tar.bz2 ghdl-87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869.zip | |
testsuite/gna: add tests, close #2116
Diffstat (limited to 'testsuite/gna/issue2116/attr5.vhdl')
| -rw-r--r-- | testsuite/gna/issue2116/attr5.vhdl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/testsuite/gna/issue2116/attr5.vhdl b/testsuite/gna/issue2116/attr5.vhdl new file mode 100644 index 000000000..63a448073 --- /dev/null +++ b/testsuite/gna/issue2116/attr5.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164;entity t is +port(s:std'r);end entity;architecture a of t is +begin i;end architecture;library i;entity b is +end entity;architecture h of b is +signal n:r(0);signal s:s(0);begin p(0);end architecture;
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