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authorTristan Gingold <tgingold@free.fr>2021-09-09 17:42:45 +0200
committerTristan Gingold <tgingold@free.fr>2021-09-10 07:34:18 +0200
commit7dc591471352c5a68eec36b0962d5cae4d47e0b7 (patch)
treedf71aa41b53b1601b7f8bc4488958fede4c8f910 /testsuite/gna/issue1843/repro.vhdl
parentead82736adbb9877f5076a3d4b31fcea32d40d2f (diff)
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testsuite/gna: add a test for #1843
Diffstat (limited to 'testsuite/gna/issue1843/repro.vhdl')
-rw-r--r--testsuite/gna/issue1843/repro.vhdl18
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/gna/issue1843/repro.vhdl b/testsuite/gna/issue1843/repro.vhdl
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index 000000000..b7a7b589e
--- /dev/null
+++ b/testsuite/gna/issue1843/repro.vhdl
@@ -0,0 +1,18 @@
+ENTITY repro IS
+ GENERIC(WIDTH : positive := 32);
+ PORT(clk : IN bit);
+END;
+
+ARCHITECTURE rtl OF repro IS
+ CONSTANT UPPER_LIMIT : bit_vector(WIDTH DOWNTO 0) := (OTHERS => '1');
+ SIGNAL count : bit_vector((WIDTH-1) DOWNTO 0);
+BEGIN
+
+ p_counter : PROCESS (clk)
+ BEGIN
+ IF ('0', count) /= UPPER_LIMIT then
+ count(0) <= '1';
+ END IF;
+ END PROCESS;
+
+END ARCHITECTURE rtl;