Add testcase for issue17.

1 files changed, 31 insertions, 0 deletions

diff --git a/testsuite/gna/issue17/cond_assign_var.vhdl b/testsuite/gna/issue17/cond_assign_var.vhdl
new file mode 100644
index 000000000..c6e4af87f
--- /dev/null
+++ b/testsuite/gna/issue17/cond_assign_var.vhdl
@@ -0,0 +1,31 @@
+library ieee ; 

+use ieee.std_logic_1164.all ; 

+use std.textio.all ; 

+

+entity cond_assign_var is

+end entity cond_assign_var ;

+

+architecture doit of cond_assign_var is

+  signal Clk : std_logic := '0'  ; 

+  signal Y : std_logic ; 

+begin

+  Clk <= not Clk after 10 ns ; 

+  

+  process (Clk)

+    variable A : std_logic ; 

+  begin

+    A := 'H' when Clk = '1' else 'L' ;

+    Y <= A ; 

+--    Y <= 'H' when Clk = '1' else 'L' ;

+  end process ;

+

+--    Y <= 'H' when Clk = '1' else 'L' ;

+    

+  process

+  begin

+    wait for 500 ns ; 

+    std.env.stop ;

+  end process ; 

+end architecture doit ; 

+

+