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authorTristan Gingold <tgingold@free.fr>2021-03-18 18:39:22 +0100
committerTristan Gingold <tgingold@free.fr>2021-03-18 18:39:22 +0100
commit9a80de30f485c9af8aaeb9eeb9ec986c7fffa6f8 (patch)
tree775c6e3fdb50e19a714e34a72f64bcd7c6302d6f /testsuite/gna/issue1687/ent.vhdl
parentc4256d931efe445aab9153486c9e5082d23056eb (diff)
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testsuite/gna: add test for #1687
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+use work.pack_RC_Add_n_F.all;
+
+entity RC_Add_n_F is
+ generic(n : natural := 4);
+ port(A, B : in bit_vector(n-1 downto 0); Cin: in bit; Sum: out bit_vector(n-1 downto 0); Cout: out bit);
+end RC_Add_n_F;
+
+architecture Arch_RC_Add_n_F of RC_Add_n_F is
+ signal result: bit_vector(n downto 0);
+begin
+ -- result <= RC_Add_n(A(3 downto 0), B, Cin); -- Works
+ -- result <= RC_Add_n(A => A(3 downto 0), B => B, Cin => Cin); -- Works
+ result <= RC_Add_n(A(3 downto 0) => A(3 downto 0), B => B, Cin => Cin); -- Fails
+ Sum <= result(n-1 downto 0);
+ Cout <= result(n);
+end Arch_RC_Add_n_F;