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| author | Tristan Gingold <tgingold@free.fr> | 2021-08-22 22:16:05 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-08-23 07:24:03 +0200 |
| commit | 4c3d63af12bcd1a346696b1ce9a226f5b83456ad (patch) | |
| tree | 0d92ba4fc8e80c27c974b56a7a63e8fe615b4bc1 /testsuite/gna/issue1672/repro.vhdl | |
| parent | a20bce35a9ee05e8e2a4599e510d08fe2fd9ebc5 (diff) | |
| download | ghdl-4c3d63af12bcd1a346696b1ce9a226f5b83456ad.tar.gz ghdl-4c3d63af12bcd1a346696b1ce9a226f5b83456ad.tar.bz2 ghdl-4c3d63af12bcd1a346696b1ce9a226f5b83456ad.zip | |
testsuite/gna: add test for #1672
Diffstat (limited to 'testsuite/gna/issue1672/repro.vhdl')
| -rw-r--r-- | testsuite/gna/issue1672/repro.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/gna/issue1672/repro.vhdl b/testsuite/gna/issue1672/repro.vhdl new file mode 100644 index 000000000..ad4ee55ea --- /dev/null +++ b/testsuite/gna/issue1672/repro.vhdl @@ -0,0 +1,20 @@ +entity repro_sub is + generic (num_ports : integer); + port (clocks : bit_vector(0 to num_ports - 1)); +end entity; + +architecture a of repro_sub is +begin +end architecture; + + +entity repro is +end entity; + +architecture a of repro is + signal clock : bit := '0'; +begin + repro_sub_inst : entity work.repro_sub + generic map (num_ports => 4) + port map (clocks => (others => clock)); +end architecture; |