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| author | Tristan Gingold <tgingold@free.fr> | 2021-09-07 21:32:51 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-09-07 21:32:51 +0200 |
| commit | dd340008ba64eaf2a48e4bbda8011f757df9539c (patch) | |
| tree | 52f8278fb4835cc7862b30634d4e8258716e1c25 /testsuite/gna/issue1523/repro.vhdl | |
| parent | 265cc22a5ca65c552d7e9c2b55f800787254c687 (diff) | |
| download | ghdl-dd340008ba64eaf2a48e4bbda8011f757df9539c.tar.gz ghdl-dd340008ba64eaf2a48e4bbda8011f757df9539c.tar.bz2 ghdl-dd340008ba64eaf2a48e4bbda8011f757df9539c.zip | |
testsuite/gna: add a test for #1523
Diffstat (limited to 'testsuite/gna/issue1523/repro.vhdl')
| -rw-r--r-- | testsuite/gna/issue1523/repro.vhdl | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/testsuite/gna/issue1523/repro.vhdl b/testsuite/gna/issue1523/repro.vhdl new file mode 100644 index 000000000..edf10bf26 --- /dev/null +++ b/testsuite/gna/issue1523/repro.vhdl @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; + +package package1 is + type InnerRecordType is record + inner2a : std_logic_vector(3 downto 0); -- NOTE: deleting me makes test pass + inner2b : std_logic_vector; + end record; + + type OuterRecordType is record + inner1 : InnerRecordType; + end record; +end package; + +library ieee; +use ieee.std_logic_1164.all; + +use work.package1.all; + +entity entity1 is + generic (WIDTH : integer); + port (port1 : in OuterRecordType(inner1(inner2b(WIDTH-1 downto 0)))); +end entity; + +architecture arc of entity1 is +begin + process is + begin + wait for 10 ns; + assert port1.inner1.inner2b = x"ffff" severity failure; + report "PASS"; + wait; + end process; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +use work.package1.all; + +entity ghdl_bug_repro is +end entity; + +architecture arc of ghdl_bug_repro is + constant WIDTH : integer := 16; + + signal sig1 : OuterRecordType(inner1(inner2b(WIDTH-1 downto 0))); +begin + ENTITY1_INST : entity work.entity1 generic map (WIDTH => WIDTH) port map (port1 => sig1); + sig1.inner1.inner2b <= x"ffff"; +end architecture; |