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author | Tristan Gingold <tgingold@free.fr> | 2020-04-28 06:05:26 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-28 06:05:26 +0200 |
commit | cf7be93092511d3c05b6d81b989c7ed3103d5fa3 (patch) | |
tree | d423ed1cab928a701ba87aba1cf7678489c1a67c /testsuite/gna/issue1269/ent93.vhdl | |
parent | 4de2876f23330b155aac45a223a165c8334f4051 (diff) | |
download | ghdl-cf7be93092511d3c05b6d81b989c7ed3103d5fa3.tar.gz ghdl-cf7be93092511d3c05b6d81b989c7ed3103d5fa3.tar.bz2 ghdl-cf7be93092511d3c05b6d81b989c7ed3103d5fa3.zip |
testsuite/gna: add a test for #1269
Diffstat (limited to 'testsuite/gna/issue1269/ent93.vhdl')
-rw-r--r-- | testsuite/gna/issue1269/ent93.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/gna/issue1269/ent93.vhdl b/testsuite/gna/issue1269/ent93.vhdl new file mode 100644 index 000000000..28fbf1aca --- /dev/null +++ b/testsuite/gna/issue1269/ent93.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent93 is +end ent93; + +architecture arch of ent93 is +begin + process + variable color: bit_vector(2 downto 0); + variable lcol: std_logic_vector(31 downto 0); + begin + lcol := ( + 23 downto 16 => color(2), + 15 downto 8 => color(1), + 7 downto 0 => color(0), + others=> '0' + ); + wait; + end process; +end architecture; |