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author | Tristan Gingold <tgingold@free.fr> | 2021-09-09 18:05:10 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-09-10 07:34:19 +0200 |
commit | ae3e6932f7cecfce0dce4777644fc29040886651 (patch) | |
tree | 33cdf11b000d112dff30f7ca1a8f2b0094462d30 /testsuite/gna/issue1129/test.vhdl | |
parent | f30826bdd87ac8191cc03f30fd00ba170f0f6c55 (diff) | |
download | ghdl-ae3e6932f7cecfce0dce4777644fc29040886651.tar.gz ghdl-ae3e6932f7cecfce0dce4777644fc29040886651.tar.bz2 ghdl-ae3e6932f7cecfce0dce4777644fc29040886651.zip |
testsuite/gna: add a test for #1129
close #1129
Diffstat (limited to 'testsuite/gna/issue1129/test.vhdl')
-rw-r--r-- | testsuite/gna/issue1129/test.vhdl | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/testsuite/gna/issue1129/test.vhdl b/testsuite/gna/issue1129/test.vhdl new file mode 100644 index 000000000..7bcaeea54 --- /dev/null +++ b/testsuite/gna/issue1129/test.vhdl @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ent is + generic( + BITS : positive); + port( + input : in unsigned(BITS - 1 downto 0)); +end entity; + +architecture rtl of ent is +begin +end architecture; + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is +end entity; + +architecture rtl of test is + constant MAX : positive := 7; + signal input : u_unsigned(MAX - 1 downto 0); +-- constant CONST : unsigned := to_unsigned(MAX, input); +begin + ent : entity work.ent + generic map( + BITS => MAX) + port map( + input => to_unsigned(MAX, input)); + --input => CONST); +end architecture; |