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| author | Tristan Gingold <tgingold@free.fr> | 2020-08-04 19:20:43 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-08-04 19:20:43 +0200 |
| commit | 05bbe09ac1f6fc9243bca3de7e156fee155e8184 (patch) | |
| tree | 219e48a0c724aa03b59f46531d238b753f79ae8e /testsuite/gna/issue1128/test.vhdl | |
| parent | 4dd28fa272167fd8c02a8f95ab8bcb10f3ea9601 (diff) | |
| download | ghdl-05bbe09ac1f6fc9243bca3de7e156fee155e8184.tar.gz ghdl-05bbe09ac1f6fc9243bca3de7e156fee155e8184.tar.bz2 ghdl-05bbe09ac1f6fc9243bca3de7e156fee155e8184.zip | |
testsuite/gna: add a test for #1128.
Close #1128
Diffstat (limited to 'testsuite/gna/issue1128/test.vhdl')
| -rw-r--r-- | testsuite/gna/issue1128/test.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/gna/issue1128/test.vhdl b/testsuite/gna/issue1128/test.vhdl new file mode 100644 index 000000000..5de688c2d --- /dev/null +++ b/testsuite/gna/issue1128/test.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is + port( + input : in unsigned := "0011"); +end entity; + +architecture rtl of test is + signal copy : input'subtype; +begin +end architecture; + |