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| author | Tristan Gingold <tgingold@free.fr> | 2018-11-16 21:00:12 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-11-16 21:00:12 +0100 |
| commit | 342971aa2920aa01a1b636e892ef709e6abfdd37 (patch) | |
| tree | f322c6db85cc9fe8f08ee9bf9c5862011ffb005d /testsuite/gna/bug090/crash12.vhdl | |
| parent | ad252b4268f855b7df53092826b6f6a57ce4c4e3 (diff) | |
| download | ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.tar.gz ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.tar.bz2 ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.zip | |
Add bug090.
Diffstat (limited to 'testsuite/gna/bug090/crash12.vhdl')
| -rw-r--r-- | testsuite/gna/bug090/crash12.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/gna/bug090/crash12.vhdl b/testsuite/gna/bug090/crash12.vhdl new file mode 100644 index 000000000..2724436bb --- /dev/null +++ b/testsuite/gna/bug090/crash12.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity clkgen is + generic (period : time := 10 ns); + port (signal clk : out std_logic := '0'); +end clkgen; + +architecture behav of clkgen is +begin + process + begin + "xxx" . null; + end process; +end behav; + |