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author | Tristan Gingold <tgingold@free.fr> | 2017-10-29 09:46:45 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-10-29 09:49:01 +0100 |
commit | 6ecc19f129a9cb25c9edb0fab18f56f5d0914a40 (patch) | |
tree | 305ce0d6495d010b130fbf7a1bdd9eea859e4906 /testsuite/gna/bug077/repro6.vhdl | |
parent | 6a5dd8aa7565e497b9ec19f6a95dd236a50f1628 (diff) | |
download | ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.tar.gz ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.tar.bz2 ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.zip |
Add test cases for individual assocs.
Diffstat (limited to 'testsuite/gna/bug077/repro6.vhdl')
-rw-r--r-- | testsuite/gna/bug077/repro6.vhdl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/gna/bug077/repro6.vhdl b/testsuite/gna/bug077/repro6.vhdl new file mode 100644 index 000000000..f2d96169d --- /dev/null +++ b/testsuite/gna/bug077/repro6.vhdl @@ -0,0 +1,32 @@ +entity repro6 is +end repro6; + +architecture behav of repro6 is + type my_rec is record + a : bit; + w : bit_vector (1 to 3); + end record; + + procedure check (signal v : my_rec) is + begin + assert v.a = '0' and v.w = "001"; + end check; + + procedure pack (signal a : bit; signal w : bit_vector) is + begin + check (v.a => a, + v.w => w); + end pack; + + signal sa : bit; + signal sw : bit_vector (1 to 2); +begin + process + begin + sa <= '0'; + sw <= "01"; + wait for 0 ns; + pack (sa, sw); + wait; + end process; +end; |